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A mixed-precision memristor and SRAM compute-in-memory AI processor

Nature volume 639, pages 617–623 (2025)Cite this article

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Abstract

Artificial intelligence (AI) edge devices1,2,3,4,5,6,7,8,9,10,11,12 demand high-precision energy-efficient computations, large on-chip model storage, rapid wakeup-to-response time and cost-effective foundry-ready solutions. Floating point (FP) computation provides precision exceeding that of integer (INT) formats at the cost of higher power and storage overhead. Multi-level-cell (MLC) memristor compute-in-memory (CIM)13,14,15 provides compact non-volatile storage and energy-efficient computation but is prone to accuracy loss owing to process variation. Digital static random-access memory (SRAM)-CIM16,17,18,19,20,21,22 enables lossless computation; however, storage is low as a result of large bit-cell area and model loading is required during inference. Thus, conventional approaches using homogeneous CIM architectures and computation formats impose a trade-off between efficiency, storage, wakeup latency and inference accuracy. Here we present a mixed-precision heterogeneous CIM AI edge processor, which supports the layer-granular/kernel-granular partitioning of network layers among on-chip CIM architectures (that is, memristor-CIM, SRAM-CIM and tiny-digital units) and computation number formats (INT and FP) based on sensitivity to error. This layer-granular/kernel-granular flexibility allows simultaneous optimization within the two-dimensional design space at the hardware level. The proposed hardware achieved high energy efficiency (40.91 TFLOPS W−1 for ResNet-20 with CIFAR-100 and 28.63 TFLOPS W−1 for MobileNet-v2 with ImageNet), low accuracy degradation (<0.45% for ResNet-20 with CIFAR-100 and for MobilNet-v2 with ImageNet) and rapid wakeup-to-response time (373.52 μs).

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Fig. 1: Overview of proposed heterogeneous INT–FP hybrid-mode and memristor-SRAM-digital mix-CIM AI edge processor.
Fig. 2: Overview of the proposed layer-based INT–FP hybrid-mode controller and hybrid-mode implementation.
Fig. 3: Overview of the proposed memristor-SRAM-digital mix-CIM structure.
Fig. 4: Measurement results and demonstration of the proposed AI edge device.

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Data availability

The datasets that we used for benchmarking are publicly available in refs. 51,52,53,55,56,57. Other data that support the findings of this study can be made available by the corresponding author on request after TSMC management approval.

Code availability

The codes that support the findings of this study are not available but exceptions for non-commercial use might be made on request after TSMC management approval.

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Acknowledgements

We acknowledge support from National Tsing Hua University (NTHU), TSMC Corporate Research (TSMC-CR), TSMC Design Technology Platform (TSMC-DTP), TSMC More-than-Moore Technologies (TSMC-MtM), TSMC-NTHU Joint Developed Project (JDP) and the National Science and Technology Council (NSTC) of Taiwan. We also acknowledge contributions from TSMC colleagues H.-S. P. Wong, H. Chuang, W. T. Chu and K. C. Huang.

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  1. These authors contributed equally: Win-San Khwa, Tai-Hao Wen, Hung-Hsi Hsu

Authors and Affiliations

  1. Taiwan Semiconductor Manufacturing Company Limited (TSMC), Hsinchu, Taiwan, Republic of China

    Win-San Khwa, Hung-Hsi Hsu, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang & Meng-Fan Chang

  2. Department of Electrical Engineering, National Tsing Hua University (NTHU), Hsinchu, Taiwan, Republic of China

    Tai-Hao Wen, Hung-Hsi Hsu, Wei-Hsing Huang, Yu-Chen Chang, Ting-Chien Chiu, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Wei-Ting Hsu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang & Meng-Fan Chang

  3. Department of Life Science, National Tsing Hua University (NTHU), Hsinchu, Taiwan, Republic of China

    Chung-Chuan Lo

  4. Department of Physics, National Chung Hsing University (NCHU), Taichung, Taiwan, Republic of China

    Mon-Shu Ho

  5. Taiwan Semiconductor Manufacturing Company Limited (TSMC), San Jose, CA, USA

    Ashwin Sanjay Lele

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Contributions

W.-S.K., T.-H.W., H.-H.H., W.-H.H., Y.-C.C., T.-C.C., Z.-E.K., Y.-H.C., H.-J.W., W.-T.H. and M.-F.C. designed the hybrid-mode mix-CIM AI edge processor and test chip. W.-S.K., T.-H.W., H.-H.H., W.-H.H., Y.-C.C., T.-C.C., Z.-E.K., Y.-H.C., H.-J.W., W.-T.H., C.-C.L., R.-S.L., C.-C.H., K.-T.T., M.-S.H., A.S.L. and M.-F.C. contributed ideas. W.-S.K., T.-H.W., H.-H.H., W.-H.H., Y.-C.C., T.-C.C., Z.-E.K., Y.-H.C., H.-J.W., W.-T.H. and S.-H.T. built the test measurement system and testing flow for the hybrid-mode mix-CIM AI edge processor. W.-S.K., T.-H.W., H.-H.H., W.-H.H., Y.-C.C., T.-C.C., Z.-E.K., Y.-H.C., H.-J.W. and W.-T.H. performed analysis and measurements of the hybrid-mode mix-CIM AI edge processor. C.-C.C., Y.-D.C., T.-Y.J.C. and M.-F.C. managed the project.

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Correspondence to Meng-Fan Chang.

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Extended data figures and tables

Extended Data Fig. 1 Experiment platform and timing-extraction circuit.

a, Experiment platform used to assess the proposed memristor-SRAM CIM-fusion processor, including data generator, logic analyser, oscilloscope, power supply and analogue voltage supply. b, On-chip timing-extraction circuit and experiment methods used to measure wakeup-to-response latency. c, Illustration of the signal involving measurement of the wakeup-to-response latency. d, Measured waveform indicating wakeup-to-response latency using a ResNet-20 model trained for the FLAME dataset.

Extended Data Fig. 2 Trade-off between accuracy and energy efficiency under various input and weight formats.

a, Measured energy efficiency under various input and weight formats using a ResNet-20 model trained for CIFAR-100. b, Inference accuracy using a ResNet-20 model trained for CIFAR-100 versus software baseline under FP16. c, FoM performance as a function of input and weight formats. FoM = energy efficiency/inference accuracy degradation.

Extended Data Fig. 3 Trade-off between accuracy and energy efficiency under various mix-CIM configurations.

a, Breakdown of CIM architectures (memristor-CIM, SRAM-CIM and tiny-digital unit). b, Measured energy efficiency and inference accuracy degradation of various computing architectures using a ResNet-20 model trained for CIFAR-100. c, Normalized deviation in the output value of each layer in a ResNet-20 model trained for the CIFAR-100 dataset. d, FoM as a function of mix-CIM configuration. FoM = energy efficiency/inference accuracy degradation.

Extended Data Fig. 4 Implementation of memristor-CIM and SRAM-CIM.

a, The memristor-CIM performs partial dot-product operations in the cell array by inducing cell current in the memristor device and accumulating cell current on the BL. The 5-bit-resolution ADC converts BL current from the analogue domain to the digital domain and the accumulator combines the results from the weight MSB column to the LSB column across input cycles to generate DPVs. b, Implementation of SRAM-CIM using a mux-based compute unit for dot-product operations with no accuracy loss.

Extended Data Fig. 5 Illustration of the proposed 2D-PVA-DA scheme.

a, Conventional memristor-CIM using a consistent number of accumulations (the number of WLs that are turned on in a single cycle) across various input place values and weight place values. b, The proposed 2D-PVA-DA adjusts the number of accumulations according to the place value of inputs and weights to increase the overall number of accumulations. c, This scheme reduced the operation cycle counts by 42% in memristor-CIM.

Extended Data Fig. 6 Layer-wise configurations for various applications and measurement results demonstrating the efficacy of the proposed AI edge processor when applied to keyword spotting and visual wake word detection.

a, Layer-wise configuration of the ResNet-20 model trained for CIFAR-100 using hybrid mode and mix-CIM. b, Layer-wise configuration of the MobileNet-v2 model trained for ImageNet using hybrid mode and mix-CIM. c, Breakdown of computation types (INT and FP) on the left axis and CIM architectures (memristor-CIM, SRAM-CIM and tiny-digital unit) on the right axis. d, Inference accuracy and energy efficiency across use scenarios.

Extended Data Fig. 7 Comparison of proposed 2DQA scheme versus previous works.

a, Processing of the pretrained model by the proposed 2DQA scheme. b, Error injection was used to obtain concise guidelines by which to determine the sensitivity of each layer for use in deriving a usable configuration without having to assess all possible combinations iteratively. c, 2DQA scheme outperformed all previous mixed-precision architectures in terms of inference accuracy when applied to the complex ImageNet dataset. Data from refs. 11,47,60,61.

Extended Data Fig. 8 Illustration of pre-alignment process for FP inputs and weights and comparison of alignment methods for FP operations.

a, During the pre-alignment process, the FP format is converted to the fixed-point format to facilitate subsequent processing. b, Comparison of different alignment methods: product alignment, input alignment, input-wise and layer-wise weight separate alignment and the proposed input-wise and kernel-wise weight separate alignment. c, Simulated energy consumption by memristor-CIM macro under various alignment methods. d, Inference accuracy as a function of bit width under various alignment methods.

Extended Data Fig. 9 Characteristics and specifications of the proposed memristor device.

The characteristics of the proposed memristor, including the underlying technology, memristor cell size, set/reset voltages, read voltage, normalized resistance state of weights, normalized conductance state of weights and dimensions of memristor banks.

Extended Data Table 1 Comparison of NVM-based processors and macros
Full size table

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Khwa, WS., Wen, TH., Hsu, HH. et al. A mixed-precision memristor and SRAM compute-in-memory AI processor. Nature 639, 617–623 (2025). https://doi.org/10.1038/s41586-025-08639-2

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