Extended Data Fig. 1: Microscopic images of metal interconnections and a CMOS inverter.
From: A flexible digital compute-in-memory chip for edge intelligence
a, Cross-sectional SEM image of the metallization layers (scalable to 5 metallization layers) and dielectric layers. M1 and M3 serve as the gate and source/drain metals of the TFT, respectively. b, Cross-sectional SEM images of an LTPS-TFT inverter and TEM image of the gate stacks with corresponding energy-dispersive spectroscopy (EDS). The cross-sectional TEM image and corresponding EDS analysis reveal well-defined multilayer gate stacks and uniform elemental distributions, contributing to the high mobility, excellent reliability, and large-scale uniformity of TFT chips. Scale bars, 1 μm (a); 2 μm (b, top inset); and 300 nm (b, bottom inset).
