Abstract
Flexible electronics, coupled with artificial intelligence, hold the potential to revolutionize robotics, wearable and healthcare devices1, human–machine interfaces2, and other emerging applications3,4. However, the development of flexible computing hardware that can efficiently execute neural-network-inference tasks using parallel computing remains a substantial challenge5. Here we present FLEXI, a thin, lightweight and robust flexible digital artificial intelligence integrated circuit to address this challenge. Our approach uses process-circuit-algorithm co-optimization and a digital dynamically reconfigurable compute-in-memory architecture. Key features include clock frequency operation of up to 12.5 MHz and power consumption as low as 2.52 mW, all while achieving subdollar-per-unit cost and an operational circuit yield of between approximately 70% and 92%. Our circuits can perform 1010 fixed and random multiplications without error, withstand over 40,000 bending cycles and maintain stable performance for a period exceeding 6 months. A one-shot on-chip neural network deployment eliminates the power consumption and latency associated with sequential weight writing, achieving up to 99.2% accuracy in temporal arrhythmia detection tasks on a single 1-kb chip. In addition, FLEXI demonstrates over 97.4% accuracy in human daily activity monitoring using multimodal physiological signals.
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Data availability
The data that support the plots within this paper and other finding of this study are available via Zenodo at https://doi.org/10.5281/zenodo.14268923 (ref. 51).
Code availability
The code that supports the plots within this paper and other finding of this study is available via GitHub at https://github.com/Adai2020/FLEXI.
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Acknowledgements
This work is supported in part by the National Key R&D Program of China (2022YFB3204100 and 2021YFC3002200), in part by the National Natural Science Foundation of China (U20A20168, U25A6021, 92580209, 51861145202, 92364102 and 92264201), in part by QYJS-2022-1600-B, in part by the Beijing National Research Center Youth Innovation Foundation (BNR2024RC01002), and in part by Beijing Nova Program. We thank the support from JCCDFSIT and STIC. The study protocol was thoroughly reviewed and approved by the ethical committee of Tsinghua University (project number THU01-20240160), and informed consent was obtained from all participants for all experiments. We thank L. Q. Tao, J. Pan and J. J. Yin for their suggestions during the revision of this article.
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T.-L.R., H.L. and B.Y. conceived of the concept and supervised the project. A.Y., J.Y. Y.F., P.S., H.L and B.Y. designed the chip architecture and circuits. A.Y. and J.Y. implemented physical layout of the chip. X.X. and F.Q. supervised the fabrication process, flexible PCB bonding and stability tests. A.Y., J.Y. E.Z., J.S. and Z.H. developed the test system. A.Y., J.Y., P.S., E.Z., J.S. and Z.P. developed the software tool chain, implemented the AI models on the chip and conducted all chip measurements. A.Y., J.Y., E.Z., J.S., Q.Z., D.L., Z.H. and Y.D. contributed to the test and analysis of chips. A.Y., Q.Z., J.S., X.L., Z.P. and H.L. conducted the data collection, data preprocess and interpretation of daily activities. Y.Y. and T.S. provided guidance on chip testing and text modification. All authors contributed to the writing and editing of the paper.
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Extended data figures and tables
Extended Data Fig. 1 Microscopic images of metal interconnections and a CMOS inverter.
a, Cross-sectional SEM image of the metallization layers (scalable to 5 metallization layers) and dielectric layers. M1 and M3 serve as the gate and source/drain metals of the TFT, respectively. b, Cross-sectional SEM images of an LTPS-TFT inverter and TEM image of the gate stacks with corresponding energy-dispersive spectroscopy (EDS). The cross-sectional TEM image and corresponding EDS analysis reveal well-defined multilayer gate stacks and uniform elemental distributions, contributing to the high mobility, excellent reliability, and large-scale uniformity of TFT chips. Scale bars, 1 μm (a); 2 μm (b, top inset); and 300 nm (b, bottom inset).
Extended Data Fig. 2 Equivalent circuit diagrams of FLEXI in memory and compute modes and performance comparison of FLEXI chip family with varying capacities on standard benchmarks.
a, Memory mode: write. b, Memory mode: read. c, Compute mode. The memory mode activates one row to enable WDs and SAs for data writing and reading, while the compute mode activates one row per compartment, enabling parallel VMM execution. d, Standard benchmarks including MIT-BIH arrhythmia, the Modified National Institute of Standards and Technology (MNIST), Google Speech Command (GSC), and Fashion-MNIST (FMNIST). All accuracy data is provided in Supplementary Table 2.
Extended Data Fig. 3 Single-ended writing and reading performance of an SRAM cell, microscope image, circuit diagram, and truth table of an RLPU, and energy breakdown analysis of FLEXI-4 in compute mode.
a,b, Probing test (a) represents writing ‘1’ in BL, and test (b) represents writing ‘0’, indicating the single-ended writing and reading in SRAM. The BL is driven as input, and the BLB is monitored as output. The observation that BLB follows BL suggests that the SRAM cell exhibits reliable switching behavior with low latency, even under a single-ended write of 10 ns. c, Microscope image and circuit diagram of an RLPU. d, Truth table of an RLPU. e, Energy breakdown of FLEXI-4 for a single multiplication at VDD = 5.5 V. Scale bars, 10 μm (c, top and bottom insets).
Extended Data Fig. 4 Data preprocessing pipeline of physiological data, equivalent reuse frequencies and distribution of weights deployed on FLEXI-1, and the confusion matrix of a four-channel 1D CNN.
a, Data preprocessing including filtering, peak detection, and smoothing. b, Equivalent reuse frequencies represent the square root of the computational time per bit of weight during a single on-chip inference. c, Distribution of weights visualizing the compute workload and allocation of weights. Weights computed more frequently are deployed in rows adjacent to the RLPU, where they exhibit better computational performance. d, Confusion matrix illustrating the classification accuracy for predicting each type of routine activity in the test set.
Supplementary information
Supplementary Information (download PDF )
Supplementary information providing extended descriptions of device performance, chip architecture, operation evaluation and system-level implementations supporting the findings presented in this work. This file contains Supplementary Notes 1–11, Figs. 1–47, Tables 1–10 and References.
Supplementary Data File 1 (download TXT )
This file contains the log of the endurance test performed using randomly generated input data. The log records more than 104 sets of hexadecimal random inputs applied to the FLEXI-4 chip. For each input set, the file documents the detailed computation counters and the corresponding timestamps for 106 multiplication operations.
Supplementary Video 1 (download MP4 )
Mechanical bending test of FLEXI-4. A FLEXI-4 chip was mounted on a bending mould with a bending radius of 1 mm and subjected to repeated bending between 0° and 180°. Both the bending mould and the automated bending system were supplied by Mars Testing Technology. The system also recorded the total number of bending cycles. The folding speed was maintained at 30–40 cycles per minute. The electrical performance of FLEXI-4 was measured before and after bending at VDD = 5 V, showing only minimal degradation.
Supplementary Video 2 (download MP4 )
Mechanical rolling test of FLEXI-1 on glass rods. A FLEXI-1 chip was repeatedly rolled around glass rods with small radii, down to 2 mm. In the video, the left panel shows the FLEXI-1 device connected to a testing PCB as it is wrapped and released on the glass rod. The right panel shows the testing program running on the testing PCB, which delivers a sequence of digital inputs to the chip. Each value is iteratively computed 10,000 times, and any resulting errors are automatically recorded. No computation errors were observed during the rolling process. Electrical measurements taken before and after rolling show only negligible variations, confirming the excellent operational stability of the FLEXI-1 chip.
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Yan, A., Yan, J., Shen, P. et al. A flexible digital compute-in-memory chip for edge intelligence. Nature 649, 1165–1171 (2026). https://doi.org/10.1038/s41586-025-09931-x
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DOI: https://doi.org/10.1038/s41586-025-09931-x
