Fig. 3
The wafer-scale JJ room temperature resistance-map depending on the optimization step for 0.025 µm2 and 0.090 µm2 junction areas: (a) the resistance variation coefficient (\(\:{CV}_{{R}_{N}}\)) for JJ with static oxidation without electrodes dimensions corrections is 16% (130 × 170 nm2) and 14% (130 × 670 nm2) for 70 × 70 mm2 (49 cm2) working area; (b) using only SEBi correction reduces \(\:{CV}_{{R}_{N}}\) down 8% (0.025 µm2 JJ area) and down to 6% (0.090 µm2 JJ area) for the same working area. (c) The proposed SEBi correction and high-pressure dynamic oxidation allows decreasing the room temperature resistance variation coefficient down 6% (0.025 µm2 JJ area) and down to 4% (0.090 µm2 JJ area) for 70 × 70 mm2 working area. For 50 × 50 mm2 working area (25 cm2orange square), it is improved down to 5.2% (0.025 µm2 JJ area) and 3.4% (0.090 µm2 JJ area). For the smallest 40 × 40 mm2 working area (16 cm2green square), it is improved down to 4.1% (0.025 µm2 JJ area) and 2.3% (0.090 µm2 JJ area).
