Table 2 Temperature dependance of DIBL.
From: Structurally optimized SiC CMOS FinFET for high-temperature and low-power SoC logic integration
DIBL [mV/V] | 300 K | 400 K | 500 K | 600 K | 700 K |
|---|---|---|---|---|---|
SiC | |||||
n-type | 96.45 | 100.47 | 109.96 | 114.96 | 131.56 |
p-type | 109.82 | 115.35 | 129.97 | 135.67 | 141.52 |
Si | |||||
n-type | 90.36 | 107.07 | 120.36 | 142.80 | > 200 |
p-type | 102.53 | 114.12 | 135.47 | 154.75 | > 200 |
