Table 4 Performance analysis of 8 × 8 accurate multipliers.
Design | LUTs | RGs | SLs | CPD (ns) | Fmax (MHz) | DP (mW) |
|---|---|---|---|---|---|---|
Area optimized Xilinx IP multiplier (AOXIP) | 51 | 97 | 22 | 4.21 | 237.5 | 3.464 |
Speed optimized Xilinx IP multiplier (SOXIP) | 60 | 80 | 21 | 3.24 | 308.6 | 3.18 |
Accurate multiplier-I22 | 52 | 90 | 25 | 4.74 | 211 | 4.13 |
Accurate multiplier-II33 | 57 | 87 | 27 | 4.10 | 244 | 4.08 |
Accurate unsigned multiplier34 | 52 | 92 | 28 | 4.75 | 210.5 | 4.09 |
Accurate multiplier23 | 61 | 96 | 31 | 3.88 | 257.7 | 4.77 |
Booth multiplier35 | 58 | 90 | 26 | 3.9 | 256.4 | 3.7 |
Wallace multiplier35 | 73 | 97 | 30 | 4.7 | 212.7 | 4.4 |
Vedic multiplier36 | 91 | 112 | 34 | 3.7 | 270.2 | 4.6 |
Compressor multiplier37 | 83 | 98 | 32 | 4.6 | 217.4 | 4.5 |
Proposed | 49 | 78 | 20 | 2.99 | 334.45 | 3.01 |
