Fig. 17
From: Novel structures of chaos-based parallel multiple image encryption and FPGA implementation

The FSMs of AXI4 Controller for reading and writing operations between the SRAM and the DDR4 SDRAM.
From: Novel structures of chaos-based parallel multiple image encryption and FPGA implementation

The FSMs of AXI4 Controller for reading and writing operations between the SRAM and the DDR4 SDRAM.