Table 1 Switching states of proposed topology.
Levels (\(\times {\text{V}}_{\text{dc}}\)) | Switching states | Diode state | Effect on Capacitor | ||
|---|---|---|---|---|---|
\({\text{D}}_{1}\) | \({\text{D}}_{2}\) | Csc1 | Csc2 | ||
+ 1.00 | \({\text{S}}_{1}\), \({\text{S}}_{4}\), \({\text{S}}_{8}\),\({\text{S}}_{10}\) | 0 | 0 | ↓ | ↓ |
+ 0.75 | \({\text{S}}_{1}\), \({\text{S}}_{4}\), \({\text{S}}_{9}\),\({\text{S}}_{10}\) | 0 | 0 | ↓ | – |
+ 0.50 | \({\text{S}}_{1}\), \({\text{S}}_{3}\), \({\text{S}}_{6}\), \({\text{S}}_{8}\),\({\text{S}}_{10}\) | 0 | 1 | ↑ | ↑ |
+ 0.25 | \({\text{S}}_{1}\), \({\text{S}}_{3}\), \({\text{S}}_{6}\), \({\text{S}}_{8}\),\({\text{S}}_{11}\) | 0 | 1 | – | ↑ |
+ 0 | \({\text{S}}_{1}\), \({\text{S}}_{3}\), \({\text{S}}_{8}\),\({\text{S}}_{11}\) | 0 | 0 | ↑ | ↑ |
−0 | \({\text{S}}_{2}\), \({\text{S}}_{6}\), \({\text{S}}_{8}\),\({\text{S}}_{10}\) | 0 | 0 | ↑ | ↑ |
− 0.25 | \({\text{S}}_{2}\), \({\text{S}}_{3}\), \({\text{S}}_{6}\), \({\text{S}}_{7}\),\({\text{S}}_{10}\) | 1 | 0 | ↑ | – |
− 0.50 | \({\text{S}}_{2}\), \({\text{S}}_{3}\), \({\text{S}}_{6}\), \({\text{S}}_{8}\),\({\text{S}}_{11}\) | 1 | 0 | ↑ | ↑ |
− 0.75 | \({\text{S}}_{2}\), \({\text{S}}_{5}\), \({\text{S}}_{7}\),\({\text{S}}_{11}\) | 0 | 0 | – | ↓ |
− 1.00 | \({\text{S}}_{2}\), \({\text{S}}_{5}\), \({\text{S}}_{8}\),\({\text{S}}_{11}\) | 0 | 0 | ↓ | ↓ |
