A nine-level switched-capacitor multilevel inverter based on ANPC topology with optimized component count and suppressed charging current

Abstract

This paper presents a nine-level switched-capacitor (SC) based on ANPC inverter structure, where efficiency, compactness, and reliability are essential. Unlike conventional ANPC-based and previously reported SC topologies, the proposed structure suppresses the hard charging issue in SCs by inserting an inductor in the charging path, effectively reducing peak charging currents and associated switch stress. The inverter achieves natural self-starting and self-voltage-balancing of capacitors without additional circuitry, while requiring fewer active switches in the conduction path. These features lead to reduced component count, and minimized power losses. A peak efficiency of 96.9% is obtained at a rated power of 0.3 kW. Experimental verification confirms the theoretical predictions, demonstrating stable capacitor voltage under varying load conditions and modulation indices. Comparative analysis highlights the superiority of the proposed topology over existing SCMLIs in terms of efficiency, charging current suppression, and reduced component requirements.

Introduction

Multilevel inverters (MLIs) are widely used in the development and integration of solar PV, fuel cells, electric vehicles (EVs), and uninterruptible power supplies (UPS)¹. Compared with conventional two-level inverters, MLIs offer several advantages, including reduced dv/dt characteristics, improved efficiency, superior EMC, design flexibility, and high fault tolerance. However, achieving these benefits comes at the expense of increased circuit complexity. The requirement for multiple DC sources, switches, diodes, capacitors, and other passive components increases the size, cost, and voltage stress of the system². Conventional FC-MLIs often suffer from capacitor voltage imbalance, to overcome this, balancing circuits, voltage and current sensors, are introduced³. Moreover, these topologies typically provide only half of the DC-link voltage at the output, which necessitates additional front-end DC–DC converters or transformers for boosting, further increasing complexity and reducing efficiency⁴

Switched-capacitor (SC) MLIs have been proposed to alleviate the aforementioned issues by integrating switched capacitors into the power circuit, the inverter can achieve boosting capability, natural capacitor voltage balancing, and reduced DC source^5–7. For instance, nine-level SCMLIs have been reported in⁸, but the switches in these designs experience high voltage stress, increasing the overall cost. Similarly,⁹ presents a nine-level inverter but employs a large number of SCs and switching devices in the current loop, significantly lowering efficiency. The cascaded approach in¹⁰ generates higher voltage levels but relies on transformers, raising the overall cost. The topology in¹¹ uses series charging of capacitors but suffers from voltage imbalance due to unequal impedance in the charging paths, degrading waveform quality over time. The structure in¹² reduces voltage stress but requires 12 switches and 4 SCs, leading to higher losses. Similarly,¹³ reduces voltage stress but sacrifices efficiency, achieving only 92.8%. A notable ANPC-based nine-level SC inverter was proposed in¹⁴, which uses only nine switches, two diodes, and two SCs. However, one of the capacitors must be rated at double the DC-link voltage, which increases volume and cost. Another hybrid nine-level inverter reported in¹⁵ uses fewer switches but fails to address the hard charging of SCs, leaving switches exposed to high current spikes and high voltage ratings. The author in¹⁶ demonstrates a topology with quadruple voltage gain using fewer components, but the switches in the charging paths face severe current spikes, demanding high current ratings and raising cost. Likewise,¹⁷ proposes a single-stage nine-level topology with voltage gain, but it requires a large number of devices and an H-bridge for polarity reversal, increasing circuit complexity, stress, and cost.

To mitigate inrush currents in SCs, several soft-charging techniques have been introduced^18–21. These include resonant and quasi-resonant charging approaches, which significantly reduce charging spikes and improve efficiency. However, they often depend on a higher number of capacitors, diodes, and inductors, which increase cost, complexity, and losses. For instance,¹⁸ uses seven switches, eight diodes, three SCs, and two inductors to generate only seven levels, making it inefficient in terms of component utilization. The quasi-resonant approaches in¹⁹ and²⁰ reduce spikes but suffer from higher capacitor ripple and low efficiency. In²¹, a nine-level inverter is achieved with fewer devices, but scalability comes at the expense of additional SC cells, raising complexity. Other designs^22,23 also use inductors to reduce inrush current but rely on isolated DC sources or large numbers of switches, again increasing size and cost.

Recent studies have proposed compact seven-level^24–26 and nine-level^27–29 SCMLIs. Although some of these designs achieve a reduced number of components, most still face challenges such as high switch voltage stress and severe current spikes during capacitor charging. In particular, the ANPC-based nine-level SCMLI in²⁸ demonstrates an effective reduction in component count compared with earlier topologies but still suffers from several critical drawbacks:

• The topology in²⁸ employs two extra diodes in the charging loop compared to the proposed topology, increasing conduction losses.

• Efficiency is limited at high load power due to additional conduction devices in the charging loop.

Building upon these limitations, this paper proposes a nine-level SCMLI based ANPC that overcomes the shortcomings of²⁸. The primary contributions are as follows:

• The configuration generates nine output levels from a single DC input with fewer semiconductor devices compared with²⁸.

• The configuration requires fewer devices in the conduction paths.

• The devices in the proposed configuration experience lower TSV compared with²⁸, reducing switch stress and enabling the use of lower-rated devices.

Proposed 9 level MLI topology

Brief description of the basic multilevel unit

Figure 1 illustrates the configuration of the proposed switched capacitor-based 9-level inverter designed to generate a single-phase AC output. This topology employs a single DC input source (V_dc), 11 power switches (S₁–S₁₁) with antiparallel diodes, along with two DC-link capacitors (C₁, C₂) and two switching capacitors (C_SC1 & C_SC2) to achieve 9 distinct voltage levels. The DC-link capacitors, C₁ and C₂, function by dividing the input DC voltage into two equal parts, providing a midpoint connection that serves as the neutral point for the load. The switching capacitors, C_SC1 and C_SC2, are alternately charged by the input source and discharged through the load, facilitating the generation of the 9-level AC output waveform. A closer analysis shows that the proposed topology shares certain features with the approach reported in²⁸. However, the proposed topology uses fewer components and experiences lower voltage stress.

Fig. 1

Proposed 9-level inverter topology.

To enhance the reliability of the capacitor charging process, a soft-charging inductor is incorporated into the circuit. This inductor effectively limits the inrush current during the charging of the switched capacitors (C_SC1 & C_SC2), thereby reducing current spikes and alleviating voltage stress across the semiconductor devices. The soft-charging inductor ensures smoother capacitor voltage buildup and minimizes switching losses. The direction of current flow during different switching states is visually indicated by red lines in Fig. 2. Additionally, the charging process of the switched capacitors is illustrated in green.

Fig. 2

Positive & negative voltage states of the proposed 9-level SCMLI.

Description of output voltage states

The output voltage levels generated by the proposed topology during the positive and negative half-cycles are shown in Fig. 2(a-l) and are described as follows:

• State A (${V}_{o}=0$ ): In this state, only three switches are activated to produce a zero voltage level, as shown in Fig. 2a. During this state, capacitors (C_SC1 & C_SC2) begins to charge.

• State B (${V}_{o}=0.25{V}_{dc}$ ): As depicted in Fig. 2b, capacitor (C_SC2) continue charging, resulting in an output voltage of 0.25V_dc. In this state, the capacitor (C_SC1) is bypassed.

• State C $( {V}_{o}={0.5V}_{dc}$ ): Illustrated in Fig. 2c, this state involves a configuration where capacitors (C_SC1 & C_SC2) continue charging. The current flows through switches ${{S}_{1}, S}_{3}$, and ${S}_{10}$. Simultaneously, ${S}_{6}$ and ${S}_{8}$ are turned on to charge the switched capacitors.

• Sate D $( {V}_{o}=0.75{V}_{dc}$ ): Achieved by following the current path through switches ${{S}_{1}, S}_{4}$, ${S}_{9}$ and ${S}_{10}$, as shown in Fig. 2(d). The capacitor (C_SC1) starts discharging while capacitor (C_SC2) do not undergo any charge or discharge cycle. The output voltage level in this state is 0.75V_dc.

• State F $({V}_{o}=1.0{V}_{dc}$ ): This is the final stage of the positive output staircase waveform, as seen in Fig. 2e. during this operating mode, the capacitors (C_SC1 & C_SC2) continue discharging. The output voltage can be obtained by following the path ${{S}_{1}, S}_{4}$, C_SC1,${S}_{8}$, C_SC2 and ${S}_{10}$ to produce $1.0{V}_{dc}$.

Similar analysis can be applied over negative half cycle of the output voltage. The switching pattern used to generate 9-level output voltage presented in Table 1.

Table 1 Switching states of proposed topology.

Modulation scheme

To eliminate the necessity for synchronization among multiple triangular signals and to minimize the computational complexity associated with multi-carrier modulation schemes, single carrier sinusoidal pulse width modulation (SC-SPWM) is implemented to generate gating signals by comparing sinusoidal modulating signal with a single triangular carrier signal. Figure 3 show the evolution of the comparison zone both on the positive and negative sides of the sinusoidal reference.

Fig. 3

Modulation scheme.

Sizing of passive components

Capacitor sizing calculation

To determine the capacitance values, the maximum discharging duration (LDT) of the capacitors within the period half-cycle is taken into account²⁴.

To determine the required capacitance, the LDT must be considered. Capacitor C_SC1 discharges during the interval from θ₃ to (π − θ₁), while capacitor C_SC2 also discharges during the interval from θ₁ to (π − θ₂), as shown in Fig. 4. Hence, the capacitance of the switched capacitors calculated considering that + V_dc and − V_dc levels:

$$\begin{gathered} C_{SC1} \ge \frac{{\Delta Q_{SC1} }}{{\Delta V_{r} }}\;\; \Rightarrow \frac{{V_{dc} \int\limits_{\theta }^{\pi - \theta } {I_{p} \sin (d\theta )} }}{{\Delta V_{r} \times 2\pi f_{o} \times R_{eq} }} \hfill \\ C_{SC2} \ge \frac{{\Delta Q_{SC2} }}{{\Delta V_{r} }}\;\; \Rightarrow \quad \frac{{V_{dc} \int\limits_{{\theta_{1} }}^{{\pi - \theta_{2} }} {I_{p} \sin (d\theta )} }}{{\Delta V_{r} \times 2\pi f_{o} \times R_{eq} }} \hfill \\ \end{gathered}$$

(1)

where ∆Q_SC represents the total charge supplied by switched capacitor during half-cycle, ∆V_r denotes the allowable voltage ripple, R_eq is equivalent parasitic load impedance.

Fig. 4

DC-link and switched capacitor voltages over a half-cycle.

Selection of current limiting inductor

The equivalent circuit representing the charging current loop is shown in Fig. 5. The equivalent source voltage (V_eq), switched capacitor (C_SC), and parasitic load impedance (R_eq). During the ON switching sequence, the charging current can be expressed mathematically as;

$$i_{{L_{ch} }} = \frac{{\Delta V_{r} }}{{2\pi f_{s} L_{ch} }} \times {\text{e}}^{{(\frac{{R_{eq} }}{{2L_{ch} }}t)}} \times \sin \,(2\pi f_{s} t)$$

(2)

Fig. 5

Equivalent charging circuit.

The circuit’s resonant time period (t_r) and frequency (ω_r) are determined by the following equation²⁴:

$$t_{r} = \frac{2\pi }{{\omega_{r} }},\;\omega_{r} = \sqrt {\frac{1}{{C_{eq} \times L_{ch} }} - \left( {\frac{{R_{eq} }}{{2L_{ch} }}} \right)^{2} }$$

(3)

Hence, The required $L_{ch}$ can be determined by:

$$L_{ch} = \frac{{\sqrt {1 - \left( {\omega_{r} \times R_{eq} \times C_{eq} } \right)^{2} } }}{{2\omega_{r}^{2} \times C_{eq} }}$$

(4)

Therefore, the maximum charging current can be determined as follows:

$$i_{{L_{ch - \max } }} = \frac{\Delta V}{{L_{ch} \times \omega_{s} }} \times {\text{e}}^{{(\frac{{R_{eq} \phi }}{{L_{ch} \times \omega_{s} }})}} \times \sin (\phi )$$

(5)

where $\phi = \tan^{ - 1} \left( {\frac{{2\omega_{s} L_{ch} }}{{R_{eq} }}} \right)$.

It can be seen clearly from Eq. (5), the maximum inductor current is inversely proportional to the inductance (L_ch). In this study (L_ch = 0.25mH) is selected to limit the charging current and provide smooth charging of switched capacitor.

Power loss and harmonic distortion analysis

Power loss analysis

The proposed configuration divides its total power losses into three groups: switching losses, conduction losses, and ripple voltage⁹. As a result, the total of these loss components is a full measure of the overall energy loss in the proposed inverter.

Conduction losses

The switch’s internal resistance causes conduction losses in a semiconductor switch. The load current that flows through the switch meets the parasitic elements in its path, which are the switch’s ON state resistance (R_s), the diode’s internal resistance (R_d), the forward voltage drops (V_d) of the diode, and the capacitor’s internal resistance (R_c).

To find the conduction losses, we first calculate the conduction losses of a standard power transistor and diode. Then we apply these calculations to the multilevel inverter context. We can calculate the instantaneous conduction losses of a transistor (p_cd,SW (t)) and a diode (p_cd,D (t)) like this:

$$p_{cd,SW} = \left[ {V_{SW} + R_{SW} i(t)} \right]i(t)$$

(6)

$$p_{cd,D} = \left[ {V_{D} + R_{D} i(t)} \right]i(t)$$

(7)

where V_SW and V_D represent, respectively, on-state voltages of the semiconductor switch and diode while equivalent resistances of the semiconductor switch and diode are represented by R_SW and R_D.

The total conduction loss can be determined by

$$P_{CL} = \frac{1}{\pi }\left[ {\int\limits_{0}^{\phi } {2p_{cd,D} (t)d(\omega t)} + \int\limits_{\phi }^{\pi } {2p_{cd,SW} (t)d(\omega t)} } \right]$$

(8)

Switching losses

During the activation and deactivation phases of a semiconductor switch, switching losses occur. Throughout these processes, the switch experiences non-zero voltage and current levels, leading to the creation of switching losses in the semiconductor switch. We look at switching losses over the basic cycle. Upon completion of the turnoff period, denoted as t_ff, the voltage across the switches undergoes a linear climb to achieve V_sw. The turn-off loss of the switch can be calculated as follows:

$$\begin{gathered} P_{SL\_off} = \int\limits_{0}^{{t_{off} }} {v(t) \times i(t)} dt = \int\limits_{0}^{{t_{off} }} {\left[ {(\frac{{V_{SW,i} }}{{t_{off} }} \times t) \times ( - \frac{I}{{t_{off} }} \times (t - t_{off} ))} \right]} dt \hfill \\ = \frac{{V_{SW} \times I \times t_{off} }}{6} \hfill \\ \end{gathered}$$

(9)

where I is the current flowing through the switch before it turns OFF, V_sw,i is the off-state voltage on the switch, P_L-off,i is the turn-off loss of the switch i, and toff is the turnoff time of the semiconductor switch.

Following the turn-on period, represented as t_on, the voltage across the switches experiences a linear fall from V_sw to zero. The turn-on loss of the switch can be calculated as follows:

$$\begin{gathered} P_{SL\_on} = \int\limits_{0}^{{t_{on} }} {v(t) \times i(t)} dt = \int\limits_{0}^{{t_{on} }} {\left[ {(\frac{{V_{SW,i} }}{{t_{on} }}t) \times ( - \frac{I}{{t_{on} }} \times (t - t_{on} ))} \right]} dt \hfill \\ = \frac{{V_{SW} \times I \times t_{on} }}{6} \hfill \\ \end{gathered}$$

(10)

where P_Lon,i is the turn-on loss of the switch i, ton is the turn-on time of the switch, and I is the current through the switch after turning ON.

The average switching power loss can be written as follows:

$$P_{SL} = f_{o} \left[ {\sum\limits_{i}^{{N_{sw} }} {\left( {P_{SL\_on,i} + P_{SL\_off,i} } \right)} } \right]$$

(11)

where f_o is the fundamental frequency, N_sw is the number of switches.

Ripple voltage losses

Another important power loss in SCMLIs is the percentage of voltage ripples in the capacitor (ΔV_r). The ripple losses can be calculated by:

$$P_{RP} = \frac{{C \times \Delta V_{r}^{2} \times f_{sw} }}{2}$$

(12)

where P_RP is the ripple losses, f_sw represents the switching frequency, C is the capacitor’s capacitance, and ΔV_r is the capacitor’s voltage ripples.

The overall efficiency can now be readily estimated subsequent to the determination of the aggregate power losses within the system, facilitated by the following equation.

$$\eta = \frac{{P_{o} }}{{P_{o} + P_{SL} + P_{CL} + P_{RP} }}$$

(13)

The proposed inverter efficiency is further analyzed at different load conditions considering conduction losses, switching losses, and capacitor ripple losses using PLECS software as depicted in Fig. 6 (a). The efficiency achieved using PLECS software is relatively high 97.12% and 96.81% at an output power of 300W and 900W respectively when an inductor is used to provide soft-charging of switched capacitors. The distribution of losses in each capacitor and switch, including switching, ripple, and conduction losses, is given in Fig. 6 (b).

Fig.6

Key waveforms of (a) Proposed SCMLI efficiency, and (b) Power loss distribution.

Total harmonic distortion (THD) analysis

To check the quality of the output voltage waveform, the THD is determined using this formula:

$$THD_{V} = \frac{{\sqrt {\sum\limits_{h = 2}^{n} {V_{h}^{2} } } }}{{V_{1} }} \times 100{\raise0.5ex\hbox{$\scriptstyle 0$} \kern-0.1em/\kern-0.15em \lower0.25ex\hbox{$\scriptstyle 0$}}$$

(14)

Here, V₁ is the RMS value of the fundamental component of the output voltage, and V_h represents the RMS value of the h^th harmonic component for h ≥ 2 h. This metric provides a quantitative measure of the distortion level in the output voltage waveform generated by the proposed switched-capacitor multilevel inverter.

The output AC voltage v_o(t) of the proposed design has a total harmonic distortion (THD) that remain below 10% of the RMS value of its fundamental component. This makes sure that the inverter meets grid and power quality standards.

Results and discussion

This section analyses and discusses the simulation and experimental findings of the provided nine-level inverter.

Simulation results

The simulation outcomes of the proposed SC-MLI have been performed using PLECS software. A 300V magnitude source is employed to assess the inverter effectiveness. In generating gate pulses for the proposed inverter in this study, single carrier PWM is applied.

The steady-state waveforms for the output voltage (v_o), output current (i_o), DC-link capacitor voltages (C₁ & C₂), and SCs voltages (C_SC1 & C_SC2), are depicted in Fig. 7. The voltage waveforms clearly demonstrate nine distinct levels with step voltage of 34V and the peak value of 300V, with the capacitor voltages balanced for entire fundamental period.

Fig. 7

Waveforms of output voltage (v_o), load current (i_o), dc link voltage (v_C1 and v_C2), and voltage across the switched capacitors (v_Csc1 and v_Csc2).

The waveforms of capacitor currents under hard charging and when introducing inductor to provide soft charging are illustrated in Fig. 8. Under hard charging, the peak currents I_SC1max ​ and I_SC2max ​ reach 68.35A at rated power. When an inductor is introduced in the charging path, the peak charging currents (I_SC1max, I_SC2max)​ reduced to 13.92A at rated power. This demonstrates that the use of an inductor reduces the charging currents by approximately 5 times, effectively mitigating current spikes during capacitor charging.

Fig. 8

Capacitor currents with (a) hard charging, and (b) soft charging of switched capacitors.

Figure 9 shows the performance of the proposed inverter under step variation in load demand. shows the waveforms of output voltage (v_o), load current (i_o), supplied by the proposed topology and the voltages across the switched capacitors (C_SC1 & C_SC2) when load undergoes a step variation at time instant at t = 1.0s from (20Ω + 20mH) to (10Ω + 20mH). Due to sudden variation of R-L load, the proposed inverter is able to maintain ac output voltage without undergoing unwanted dip in voltage and the load current follows the corresponding transition. The ripple voltage of the SCs changes within 10% of its maximum value, which is acceptable. The waveform analysis reveals that the suggested inverter responds positively to variations in load. Figure 10 illustrates the variation in modulation index (m_a) from values of (m_a = 1.0 to m_a = 0.5) and from (m_a = 0.5 to m_a = 0.2) respectively. It is observed that a reducing M_a leads to a slight reduction in the magnitude of both output voltage and current. Also, the inverter is able to maintain the voltage across SCs at various m_a.

Fig. 9

Waveforms of output voltage (v_o), load current (i_o), voltage across the switched capacitors (v_Csc1 and v_Csc2) when step change in load demand from (50 Ω + 80mH) to (25 Ω + 40 mH).

Fig. 10

Waveforms of output voltage (v_o), load current (i_o), voltage across the switched capacitors (v_Csc1 and v_Csc2) when step change in modulation index from 1.0 to 0.5 to 0.2.

Experimental results

A test bench has been constructed to experimentally verify the performance of the different power electronic interfaces and the proposed inverter circuit. A laboratory prototype with a power capacity of 900W was developed, and experimental data were acquired under diverse load scenarios. Figure 11 illustrates the experimental arrangement of the proposed inverter. The DSP TMS320F28379 processor is utilized to implement the single carrier PWM, essential for generating gate pulses for the power semiconductor switches. The parameters of the proposed inverter are detailed in Table 2.

Fig. 11

Lab prototype of the proposed inverter.

Table 2 parameters of experimental setup.

The waveforms of the output voltage (v_o), load current (i_o), and voltage across the SCs (C_SC1, C_SC2) are shown in Fig. 12a when the proposed SC-MLI is powering (R-L) load. the operation of the proposed SC-MLI is validated by connecting it to constant R-L load at (20Ω + 20mH). Figure 12b depicts the equivalent waveforms of the SCs voltage and current. It can be observed that due to the use of soft-charging technique, the current on both SCs undergo smooth charging and discharging without exist of spikes in current waveform.

Fig. 12

Experimental Results (a) Output voltage, current, and dc-link voltages, (b) voltage and currents of SCs, (c) Step change in R-L load from (10 Ω + 20 mH) to (20 Ω + 20 mH), d) Step change in R-L load from (20 Ω + 20 mH) to (10 Ω + 20mH), (e)change in modulation index (m_a) from at (d) 1 to 0.5 (f) 1 to 0.2, (g) Waveforms of the output voltage While changing the reference dc-link voltages from 300 V to 350, (h), and from 300 to 300 V.

Figure 12c and d shows the output voltage (v_o), load current (i_o), and voltages across the SC when an R-L load is subjected to a step change at t = 0.25s from (10 Ω  + 20 mH) to (20 Ω + 20 mH) and from (20 Ω + 20 mH) to (10 Ω + 20 mH). Despite the rapid application of the R-L load, the generated output voltage effectively maintains the AC output voltage without an unwanted drop, and the proposed topology can maintain the SC voltages and output voltage step during sudden load changing conditions.

The performance of the proposed structure is investigated in this case under varied modulation index conditions. The waveforms of the output voltage (v_o), load current (i_o), and voltage across the SCs (C_SC1, C_SC2) where the modulation index (m_a) of the suggested inverter changes from m_a = 1.0 to m_a = 0.5 at time instant t = 0.1s shown in Fig. 12e. Its observed that the DC-link voltages were effectively balanced during these dynamic operations.

Figure 12f test the performance of proposed inverter when m_a of the suggested inverter changes from m_a = 1 to m_a = 0.2. The output voltage waveform (v_o) clearly shows that changing the modulation index leads to a drop in levels in the single-phase AC output voltage, decreasing from 9 to 2 levels. Despite this alteration, the proposed inverter continues to operate as a multilevel inverter with lower levels, and the voltage across SCs (C_SC1, C_SC2) remains balanced. This finding confirms the robust performance in response to modulation index fluctuations.

The proposed SCMLI topology was further tested under source voltage variation from 300 to 350 V and back to 300 V, as illustrated in Fig. 12g, h. The resulting output currents maintained constant peak value and their sinusoidal waveform. The results highlight its capability to maintain consistent output voltage and waveform quality despite fluctuations in the input source. This feature makes it highly suitable for renewable energy applications, where source voltage variations are common due to the intermittent nature of solar PV and wind energy.

From the Fig. 13, the voltage THD is 8.6%. Furthermore, the spectrum indicates that voltage harmonics reside around the switching frequency (i.e., 5 kHz), and hence, small filter is enough to bring even the voltage THD within the limits of IEEE-519 standards.

Fig.13

FFT analysis (up to 50th harmonic) of the output voltage.

Quantitative comparisons against conventional topologies

A comparison study is conducted in this part against some of the latest topologies^8–]29 to illustrate the feature stated in the previous section. The comparison takes into account the available number of power switches, diodes, capacitors, voltage gain, and TSV. Table 3 describes the topologies in terms of comparative parameters. In terms of number of power switches, the topologies mentioned in^8,12, and¹³ used high number of power devices. It is seen that the number of switches per voltage level of the proposed SC-MLI is among the least in comparison.

Table 3 comparison of different 9-level scmli topologies with the proposed topology.

The topology presented in ^{8,9,13,14,15,16,17,23} and ²⁹ suffer from high current spike and hence the switches are selected with high voltage ratings which increases the overall inverter cost and the overall efficiency of these topologies is relatively less due to high loss across the power switches. The topology proposed in ^12,17,21,23, and ²⁸ they use soft-charging technique which significantly decreases the current spike. However, topology in ¹² use high number of inductors to provide soft-charging which make bulky inverter structure. In contrast, the proposed topology [P] uses only one inductor with minimum inductance (0.25mH) to provide soft charging to SCs.

When it comes to the boosting factors, the gain shown in references^{8,9,12–]17,21}-^23,27, and²⁹ comes from using switches with higher voltage ratings. This raises the total standing voltage (TSV) across the switches, which makes the inverter more expensive and complicated. The proposed topology and the one in²⁸, on the other hand, are unity-gain inverters that greatly lower the voltage stress on the semiconductor devices. This kind of technique is very useful for applications with low to medium power needs where cost, size, and thermal performance are very important design criteria.

In terms of THD, the topologies presented in²⁹ and ¹⁷ exhibit lower harmonic content in the output voltage. However, the proposed inverter offers low THD compared to the other topologies listed in the comparison table, demonstrating improved output waveform quality.

The value of total Standing Voltage (TSV) is the main traditional metric employed for the evaluation of SC-MLI topologies. The topologies^{9,13,15,17,27}, and²⁹ experience higher TSV, which directly impacts their performance and results in lower efficiency compared to the proposed topology. The proposed SC-MLI topology has considerably lesser TSV than existing topologies.

The cost function (CF) of all topologies has been determined considering the device count with the voltage ratings of devices:

$$CF = \frac{{N_{IS} }}{{N_{L} }}\left[ {N_{SW} + N_{c} + N_{d} + N_{gd} + Ind + \alpha \times TSV} \right]$$

(15)

where $\alpha$ is factor which is associated with the voltage stress across the power switches, for safety, this factor considered to be 90% of the maximum allowable voltage across the switch ($\alpha = 0.9$). It is observed from Table 3 that, due to large number of power switches and switched capacitors, The CF of these topologies is high in comparison to the proposed SC-MLI [P].

Conclusion

This study introduced a novel 9-level SC-MLI featuring a single DC source and reduced number of power switches. The main features of this configuration are minimized TSV across the power switches and the integration of inductor between the input source and the SC charging loop, enabling soft charging of capacitors. This approach effectively minimizes current spikes and reduces total standing voltage stress across the power switches. A detailed comparative analysis highlights the superiority of the proposed topology over recent SC-MLIs in terms of component count, efficiency, and performance. Power loss calculations, including both switching and conduction losses, confirm high efficiency, achieving 96.96% at 300W and 96.42% at 900W. A laboratory prototype of the basic unit was developed, and the experimental validation confirmed close agreement with simulation results under various modulation indexes, demonstrating the practical viability and robustness of the proposed SC-MLI design.