Table 3 comparison of different 9-level scmli topologies with the proposed topology.

From: A nine-level switched-capacitor multilevel inverter based on ANPC topology with optimized component count and suppressed charging current

Ref

NL

H

NIS

NSW

Nd

Ngd

Nc

G

NInd

TSV (× Vdc)

CF

THD (%)

fs (Hz)

P (W)

ɳ (%)

8

9

No

1

10

2

10

3

2

0

9.75

3.75

–

5 k

350

95.50

9

9

No

2

9

2

8

1

2

0

12

6.84

11.2

3 k

900

96.3

12

9

Yes

1

12

2

12

4

2

2

16

4.93

–

5 k

508

94.90

13

9

No

1

14

0

14

2

4

0

19

3.78

15.18

2 k

250

93.23

14

9

No

1

9

2

8

2

4

0

16.5

3.98

12.96

2 k

1.0 k

98.3

15

9

No

1

8

2

8

3

2

0

20

4.33

–

2 k

500

96.4

16

9

No

1

9

1

9

2

4

0

24

4.73

–

2 k

350

95.7

17

9

Yes

1

11

2

11

2

4

1

31

6.1

8.53

50

390

95.5

21

9

Yes

1

10

0

10

2

2

1

14

3.84

–

5 k

300

92.9

22

13

Yes

1

11

0

11

3

3

0

20

3.31

–

5 k

750

93.45

23

9

No

2

14

0

10

4

4

0

42

14.62

9.29

50

10 k

98

27

9

No

1

9

2

9

2

2

0

19

4.34

–

–

–

94.18

28

9

Yes

1

10

4

9

4

1

1

8.5

3.96

–

10 k

583

98.0

29

9

No

1

13

3

13

3

4

0

21

50.9

6.9

50

1.0 k

96.0

[P]

9

Yes

1

11

2

11

4

1

1

6.75

3.88

8.6

5 k

900

96.42

  1. *NL : Number of levels; H: Quasi-resonant charging ability; NIS:  Number of input dc sources; Nsw: Number of switches; Nd:  Number of diodes; Ngd:  Number of gate drivers; G: Gain; NInd:  Number of inductors; Nc:  Number of capacitors; CF: Cost function; TSV: Total standing voltage in per unit; ɳ :  Efficiency; fs: Switching frequency
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