Fig. 5 | Scientific Reports

Fig. 5

From: Investigation of dual memory behavior in RRAM: coexistence of resistive and capacitive switching phenomena

Fig. 5

(a) Temperature distribution contour maps along Cut Plane 1 for LRS and HRS. (b) Temperature distribution at the SiOx/Si interfaces observed via Cut Plane 2 under the LRS and HRS. To clearly distinguish the temperature difference at the entire interface, the temperature caused by Joule heating in the filament was set to black. (c) Cross-sectional schematic of the device structure showing Cut Plane 1 and Cut Plane 2. (d) Equivalent circuit of the interface considering the temperature-dependent variation of Cit under the read voltage applied.

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