Table 2 Results of the implementation of the proposed EdCCp module over GF(256).

From: Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Operation

Platform

Field Size

Clock cycles

Maximum frequency(MHz)

Time

Throughput

Modular Multiplication

Virtex-5

256

129

117.809

2.04 μs

131.9 Mbps

point Operation

Virtex-5

256

646

117.809

5.48 μs

46.72 Mbps

point Multiplication

Virtex-5

256

164,730

117.809

1.4 ms

183.38 Kbps

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