Table 3 Comparison of the proffered PM unit with other designs over GF(256).

From: Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field

Design

Platform

Frequency (MHz)

Field size

Reported area

Latency (CCs)

Time (ms)

Throughput (Kbps)

Area × Time

This work

Virtex-5

117.809

256

7.9 K Slices

164.7 K

1.40

183.38

11.06

19

Virtex-5

75.43

256

393 K Slices

397.3 K

5.26

48.67

2067.18

20

Virtex-5

160

256

34.6 K LUTs

361.7 K

2.26

113.25

–

21

Virtex-7

225

256

6.8 K LUTs + 20 MLUTs

335.4 K

1.49

171.76

–

22

Virtex-7

214

256

1.3 K Slices + 2.7 K LUTs + 4 BRAMS

1584.9 K

1.80

34.57

–

23

Virtex-2

94.7

256

41.6 K Slices

252.2 K

2.66

96.56

110.66

24

Virtex-7

177.7

256

8.9 K Slices

262.7 K

1.48

173.20

13.172

27

Virtex-7

168

409

11.1 Slices

21.95 K

–

–

244

28

Virtex-6

93.23

256

6.6 K Slices

198.6 K

2.13

120.12

14.06

29

Kintex-7

156.3

256

6.5 K Slices

270.1 K

1.73

147.9

11.25

33

Virtex-7

149.23

256

7.2 K Slices

261.7 K

1.75

146

12.6

34

Virtex-7

124.2

224

5.4 K Slices

464.1 K

3.73

68.52

20.14

36

Virtex-4

20.44

256

6.4 K Slices

610.0 K

29.84

8.58

54.528

37

Agilex

203.96

256

5.4 K Slices + 15.6 K LUTs + 13.2 K FF + 128 DSP units

45.3 K

0.22

–

–

38

Agilex

200

256

–

5652

–

–

–

39

Virtex-6

121.6–125.1

256

–

–

0.30–2.94

–

18.6 k – 8.1 k

40

Virtex-7

86.6

256

12.1 k LUTs

52.8 K

0.61

420

7.4

41

Virtex-7

120

256

16,907 LUTs + 4.2 K slices

23 K

0.188

–

–

42

Virtex-5

76.31

256

8.7 K slices

300 K

3.93

65.14

34.25

43

Atrix-7

289

251

6827 slices + 24,778 LUTs

3263

11.29 µs

–

0.077

Back to article page