Abstract
Tellurium (Te) is a promising p-type semiconductor but suffers from pronounced electrical hysteresis that limits device stability. The origin of hysteresis in Te field-effect transistors is investigated, and effective suppression strategies are demonstrated. In exposed devices, large hysteresis and abrupt current switching are observed, governed by the direction and range of gate voltage sweeps rather than gate polarity, and are attributed to the dynamic reorientation of dipolar gas molecules adsorbed on the Te surface. Dielectric encapsulation using Al2O3 significantly suppresses gas-induced hysteresis, resulting in improved mobility of ~80 cm2 V-1 s-1 and an ION/IOFF ratio exceeding 105 under ambient conditions. Nevertheless, residual hysteresis associated with charge trapping persists in single-gate devices. To further stabilize channel electrostatics, a dual-gate architecture employing Al2O3 top and bottom dielectrics is implemented, achieving hysteresis below 1 V across a wide range of sweep rates and exhibiting minimal degradation under prolonged bias stress. These results establish a comprehensive understanding of hysteresis in Te and enable reliable, BEOL-compatible p-type transistors for advanced integration.
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The datasets generated and/or analyzed during the current study are not publicly available due to ongoing further studies but are available from the corresponding author on reasonable request.
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Acknowledgements
D.-H.L. acknowledges support from the National Science and Technology Council (NSTC 114-2112-M-A49-013), the NSTC T-Star Center Project: Future Semiconductor Technology Research Center (NSTC 114-2634-F-A49-001), the Ministry of Education (Yushan Scholar Program), and Taiwan Semiconductor Manufacturing Company. Y.-L.C. acknowledges support from the National Science and Technology Council, Taiwan (NSTC 113-2112-M-007-034-MY3, 114-2119-M-007-015-MBK, and 114-2628-E-007-001). We thank Integrated Service Technology (iST) for support with material characterization.
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S.-T.W., K.-W.L. and D.-H.L. conceived the idea. S.-T.W. and K.-W.L. performed the device fabrication and the measurement. S.-T.W., K.-W.L., T.-T.W. and Y.-C.C. helped the thin film growth. C.-F.C. helped the device measurement. C.-C.Chung and C.-H.L. carried out the TEM and Raman analysis. C.-Y.C. carried out the XPS analysis. S.-C.C. designed and developed the Low-T PVD tools. T.A. assisted with device simulations. S.-T.W., K.-W.L., Y.-L.C. and D.-H.L. analyzed the data. S.-T.L., Y.-F.L., I.R., T.Y.T.H., and C.-C.Cheng provided scientific guidance throughout. Y.-L.C. and D.-H.L. supervised the research. S.-T.W., K.-W.L., Y.-L.C. and D.-H.L. prepared the paper draft. All the authors contributed to the discussion and manuscript preparation and read the final manuscript.
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Wang, ST., Li, KW., Weng, TT. et al. Suppression of hysteresis in ultrathin tellurium transistors. npj 2D Mater Appl (2026). https://doi.org/10.1038/s41699-026-00686-1
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DOI: https://doi.org/10.1038/s41699-026-00686-1
