Extended Data Fig. 9: The Simulation platform and results. | Nature Electronics

Extended Data Fig. 9: The Simulation platform and results.

From: An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors

Extended Data Fig. 9

a, The modified version of hierarchical chip architecture in NeuroSim for SPNN. b, Size definition of a tile, a PE, and an array. c, Hardware-level definition of granularity. d, Accuracy curves of training process for five cases: No pruning, Block-wise, Vector-wise, Element-wise, and Index-free. e, Size, mapping and sparsity parameters of sparsified VGG-8 Net. Panel a adapted with permission from ref. 46, IEEE.

Back to article page