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An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors

Nature Electronics volume 8, pages 222–234 (2025)Cite this article

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Abstract

The fine-grained dynamic sparsity in biological synapses is an important element in the energy efficiency of the human brain. Emulating such sparsity in an artificial system requires off-chip memory indexing, which has a considerable energy and latency overhead. Here, we report an in-memory sparsity architecture in which index memory is moved next to individual synapses, creating a sparse neural network without external memory indexing. We use a compact building block consisting of two non-volatile ferroelectric field-effect transistors acting as a digital sparsity and an analogue weight. The network is formulated as the Hadamard product of the sparsity and weight matrices, and the hardware, which is comprised of 900 ferroelectric field-effect transistors, is based on wafer-scale chemical-vapour-deposited molybdenum disulfide integrated through back-end-of-line processes. With the system, we demonstrate key synaptic processes—including pruning, weight update and regrowth—in an unstructured and fine-grained manner. We also develop a vectorial approximate update algorithm and optimize training scheduling. Through this software–hardware co-optimization, we achieve 98.4% accuracy in an EMNIST letter recognition task under 75% sparsity. Simulations on large neural networks show a tenfold reduction in latency and a ninefold reduction in energy consumption when compared with a dense network of the same performance.

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Fig. 1: Dynamic sparsity in NNs.
Fig. 2: Index-free synaptic cell and device characteristics.
Fig. 3: Software–hardware co-optimization through VAU and pruning scheduling.
Fig. 4: Training an index-free MSNet on hardware.
Fig. 5: Performance projection and benchmarks.

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Data availability

Source data are available at https://doi.org/10.6084/m9.figshare.27284259.v1 (ref. 52).

Code availability

The codes used for sparse training, scheduling and simulations are available from the corresponding authors upon reasonable request.

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Acknowledgements

This work was supported by the National Key R&D Program of China (grant numbers 2022YFB4400100 (X.W.), 2023YFF1500500 (X.W.), 2021YFA1202904 (L.G.), 2022YFA1402500 (W.L.), 2021YFA0715600 (W.L.), 2023YFB2806802 (Y.F.), 2021YFB3600104 (Y.F.)), the Leading-edge Technology Program of Jiangsu Natural Science Foundation (grant numbers BK20232024 (X.W.), BK20232001 (Y.S.)), the National Natural Science Foundation of China (grant numbers T2221003 (X.W.), 61927808 (X.W.), T2322014 (Y.Z.), 62204124 (Y.Z.), 62322408 (T.L.), 62204113 (T.L.), 62104098 (Y.F.), U21B2032 (L.L), 62304101 (W.L.)), Jiangsu Funding Program for Excellent Postdoctoral Talent (grant number 20220ZB63 (W.L.)), the Natural Science Foundation of Jiangsu Province (grant number BK20220773 (T.L.), BK20230776 (W.L.), BK20210178 (Y.F.)), the Jiangsu Province Key R&D Program (BE2023009-3 (W.L.)), the Key Laboratory of Advanced Photonic and Electronic Materials, Collaborative Innovation Center of Solid-State Lighting and Energy-Saving Electronics, and the Fundamental Research Funds for the Central Universities, China. We express our gratitude to the Interdisciplinary Research Center for Future Intelligent Chips (Chip-X) and Yachen Foundation for their invaluable support. X.W. acknowledges the support by the New Cornerstone Science Foundation through the XPLORER PRIZE.

Author information

Author notes

  1. These authors contributed equally: Hongkai Ning, Hengdi Wen, Yuan Meng.

Authors and Affiliations

  1. National Laboratory of Solid State Microstructures, School of Electronic Science and Engineering and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing, China

    Hongkai Ning, Hengdi Wen, Yuan Meng, Xilu Zou, Yilin Shen, Xiai Luo, Tao Zhang, Lei Liu, Shitong Zhu, Weisheng Li, Li Li, Yi Shi & Xinran Wang

  2. School of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing, China

    Zhihao Yu

  3. Suzhou Laboratory, Suzhou, China

    Zhihao Yu, Taotao Li, Weisheng Li & Xinran Wang

  4. School of Integrated Circuits, Nanjing University, Suzhou, China

    Yuxiang Fu, Qiyue Zhao, Taotao Li, Weisheng Li & Xinran Wang

  5. Interdisciplinary Research Center for Future Intelligent Chips (Chip-X), Nanjing University, Suzhou, China

    Yuxiang Fu, Taotao Li, Weisheng Li & Xinran Wang

  6. State Key Laboratory for Organic Electronics and Information Displays, School of Materials Science and Engineering, Institute of Advanced Materials, Nanjing University of Posts and Telecommunications, Nanjing, China

    Li Gao

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Contributions

Z.Y. and X.W. supervised the project. H.N., Z.Y. and X.W. conceived the idea and designed the experiments. H.W. fabricated the array with assistance from H.N., Z.Y., W.L., X.L. and L.G. H.N. designed the software and hardware measurement system. H.W. performed the array measurement with assistance from H.N. and X.L. Y.M., Y.F., Y.S., Q.Z. and L. Li carried out the training algorithm, simulation and benchmarks. X.Z., L. Liu, S.Z. and T.L. synthesized the CVD MoS2. H.N., Z.Y. and X.W. co-wrote the manuscript with input from all authors. All authors contributed to the interpretation of data and discussion.

Corresponding authors

Correspondence to Zhihao Yu, Yuxiang Fu or Xinran Wang.

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Nature Electronics thanks Hongsik Jeong and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Trade-off dilemma of granularity in sparse training.

a, Illustration of process of sparsification and the granularity of sparse neural network (SPNN), layer-wise (the most coarse-grained), block-wise, vector-wise, and element-wise (the most fine-grained). b, The accuracy-efficiency trade-off dilemma of four granularities in sparse training. The data comes from the NeuroSim simulation of VGG8-Net on CIFAR-10 dataset, trained with IMC hardware (See more details in Methods and Extended Data Fig. 9).

Extended Data Fig. 2 Design and statistics of weight device and sparsity device.

a-b, The 3D schematic of the structure of weight device (a) and sparsity device (b). c-f, Distribution and spatial heatmap of memory window (c, d) and Ion/Ioff ratio (e, f) for all 450 weight devices in the index-free IMC array. The red lines are fitted curves by the normal distribution. g, Statistics of 16-state characteristics from 100 weight devices. On each box, the central mark indicates the median of conductance of these 100 devices on a certain weight, and the bottom and top edges of the box indicate the 25th and 75th percentiles, respectively. The whiskers extend to the most extreme data points not considered outliers. h, Collected 8-state retention curves in 100 s from 50 weight devices (The shadow are dense lines of raw data rather than any error bands).

Extended Data Fig. 3 High temperature stability of index-free hardware.

a, transfer curves of sparsity and weight- FeFETs under 25 °C, 85 °C and 125 °C. b–c, 1000s retention of sparsity (b) and weight- FeFETs (c) can projected to 10 years. d-f, 128 states with sparsity- FeFETs on or off under 25 °C (d), 85 °C (e) and 125 °C (f). g-i, output curves of potentiation process with sparsity- FeFETs on under 25 °C (g), 85 °C (h) and 125 °C (i).

Extended Data Fig. 4 Test set-up.

a, The software and hardware structure of test system. b, Program chart of auto-test of index-free IMC array. c, the picture of test system. Inset 1 (yellow border): a zoom-in of probed array in the probe station. Inset 2 (blue border): a zoom-in of the cables and probe cards inside the probe station.

Extended Data Fig. 5 The VAU.

a, Two steps (by column vectors or rows vectors) of training process with VAU. b, The mean square error (MSE) of VAU as a function of sparsity, derived from 50 runs of VAU. Errors are generated by comparing the delta weights from VAU and the accurate ones from the cell-by-cell method. On each box, the central mark indicates the median of MSE for 50 runs, and the bottom and top edges of the box indicate the 25th and 75th percentiles, respectively. The outliers are plotted individually using the ‘o’ marker symbol outside the bounds of maximum and minimum. c, The training accuracy of sparse neural network (SPNN) with conventional cell-by-cell method and VAU (with 10% write noise and 4.25% read noise introduced), derived from 20 runs of corresponding algorithms. Here, only the maximums and minimums are plotted in this box plot. See more details in Methods.

Extended Data Fig. 6 Explanation of fundamental scenarios based on a column of index-free unit cells during sparse training.

Sparsity and weight values are displayed in the purple box and blue box, respectively. The changes in specific values are colored in yellow and bolded. Cells to prune are remarked with a red dashed border, and cells to regrowth are with green ones. Active cells are colored in gray and pruned cells are colored in a much lighter gray without border. The horizontal lines across cell boxes are paths of updating (bit lines in yellow) or inference (data input lines in blue), the vertical lines across the sparsity boxes are paths of pruning/regrowth (sparsity lines in purple), and the vertical lines across the weight boxes are the paths of summarizing currents (data output lines in gray).

Extended Data Fig. 7 The array-level hardware operations and data details.

a, Array-level data flow of MSNet training. b, Synchronous output current sequence read from array made of 4000 points cut from whole data. c, Comparison between ideal current output and real current output (whole data).

Extended Data Fig. 8 Experimental results and simulation for the MSNet demonstration.

a, Accuracy and Loss curves from experiment (darker red and blue) and simulation (lighter red and blue), respectively. b, Measured and simulated weight maps of critical epochs (10, 16, 22, 28, 37, and 57). c, Inference result with representative inputs of six letters. This figure shows an example of, from left to right, written words ‘s–p–a–r–s–e’, features of conv1 layer, conv2 layer and maxpooling layer, classification output of FC layer, and finally the result of recognized words.

Extended Data Fig. 9 The Simulation platform and results.

a, The modified version of hierarchical chip architecture in NeuroSim for SPNN. b, Size definition of a tile, a PE, and an array. c, Hardware-level definition of granularity. d, Accuracy curves of training process for five cases: No pruning, Block-wise, Vector-wise, Element-wise, and Index-free. e, Size, mapping and sparsity parameters of sparsified VGG-8 Net. Panel a adapted with permission from ref. 46, IEEE.

Extended Data Fig. 10 Simulation with non-idealities and differential pairs.

a-c, Extraction of non-idealities for NeuroSim simulations including a typical multistate curve providing the nonlinearity (a), device to device variation of nonlinearity (b) and cycle to cycle variation of delta weight during updating (c). d, Training process with non-idealities for three cases: No pruning, Element-wise, and Index-free. e, Accuracy, latency and energy enhancement of index-free hardware w/o and w/ non-idealities, compared with traditional SPNN. f, The mapping schematics of weight map and sparsity map, and the structure inside the unit cell when deploying differential pairs. g, Sparse training of VGG-8 Net based on single device w/o noise, w/ noise, and differential pair w/ noise. h, Accuracy, latency and energy enhancement of index-free hardware w/o and w/ differential pairs, compared with traditional SPNN.

Supplementary information

Supplementary Video 1

The whole process of sparse training on hardware. The key components include the sparsity map and weight map (in the top left corner), an instance of input data and output images (in the bottom left corner) and the training curves of accuracy, loss and sparsity (on the right) for all epochs.

Supplementary Video 2

Visualization of 3D loss landscape of all epochs during the whole sparse training. The position of the viewport ‘camera’ is defined by an elevation of 15° and an azimuth of −60°. Of note, the axes α and β are randomly generated direction vectors to visualize the high-dimensional loss space (refer to Methods for more details).

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Ning, H., Wen, H., Meng, Y. et al. An index-free sparse neural network using two-dimensional semiconductor ferroelectric field-effect transistors. Nat Electron 8, 222–234 (2025). https://doi.org/10.1038/s41928-024-01328-4

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