Abstract
Two-dimensional (2D) semiconductors have the potential to replace silicon in next-generation electronic devices. However, despite advances in proof-of-concept device demonstrations and wafer-scale crystal synthesis, the lack of a compatible residue-free patterning technology has hindered industrialization. Here we describe a metal-stamp imprinting method for patterning 2D films into high-quality wafer-scale arrays without introducing chemical or polymer residues. A metal stamp with a three-dimensional morphology is used to form a local contact at the stamp–2D interface. The process selectively exfoliates some of the 2D material while leaving 2D arrays on the growth substrate. Microscopy and spectroscopy characterizations confirmed the clean surface and undamaged crystal structure. A statistical analysis of 100 back-gated molybdenum disulfide (MoS2) transistors and 500 top-gated logic circuits found a 20-times-lower variation of the threshold voltage compared to a reactive-ion-etching-based patterning process. The device yield on a 2-inch wafer was 97.6%.
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Data that support the plots within this paper and other findings of this study are available from the corresponding authors on reasonable request. Source data are provided with this paper.
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Acknowledgements
This work is supported by A*STAR (Grant Nos. M21K2c0116 and M24M8b0004), the Singapore National Research Foundation (Grant Nos. NRF-CRP22-2019-0004, NRF-CRP30-2023-0003, NRF2023-ITC004-001 and NRF-MSG-2023-0002) and the Singapore Ministry of Education (MOE) Tier 2 Grant (Grant No. MOE-T2EP50222-0018). H.C. acknowledges the support from the robotic AI-Scientist platform of Chinese Academy of Sciences and Anhui Outstanding Young Scientist Fund (2408085J005). Z. Liu acknowledges the support from the National Research Foundation, Singapore, under its Competitive Research Programme (CRP) (NRF-CRP22-2019-0007). This work is also supported by A*STAR MTC Programmatic Grant M23M2b0056. T.L. acknowledges the support from the National Natural Science Foundation of China (grant nos. 62322408 and 62204113). X.R.W. acknowledges support from the Singapore MOE Academic Research Fund (AcRF) Tier 3 (Grant No. MOE-MOET32023-0003) ‘Quantum Geometric Advantage’ and Tier 1 (Grant Nos. RG82/23 and RG155/24).
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W.G. and Z. Li conceived the project. Z. Li performed the experiments and data analysis. X.L. contributed to the PL and transistor measurements. J.S. contributed to the photolithography and logic-gate fabrication. X.C. contributed to the STEM characterization. Y.Z. contributed to drawing the schematics. W.C., Y.J., H.J., C.Z., Y.D., Y.L., X.R.W., H.C. and Z. Liu contributed to device fabrication. S.Y.K. and J.L. contributed to the atomistic modelling. T.L. provided the wafer monolayer MoS2 film. W.G. and Z. Li co-wrote the paper. All authors discussed the results and commented on the paper. Z. Li and X.L. contributed equally to this work.
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Nature Electronics thanks Huigao Duan, Phuong V. Pham and Yanbo Xie for their contribution to the peer review of this work.
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Supplementary Figs. 1–12.
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The process of imprinting 2D materials.
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Li, Z., Liu, X., Shi, J. et al. Residue-free wafer-scale direct imprinting of two-dimensional materials. Nat Electron 8, 571–577 (2025). https://doi.org/10.1038/s41928-025-01408-z
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DOI: https://doi.org/10.1038/s41928-025-01408-z
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