As any close reader of Nature Electronics might have observed, a year at the journal is bookended by two special issues: our technology of the year at the start, and our highlights from the IEEE International Electron Devices Meeting (IEDM) at the end. Back in January, we chose quantum computing as our technology of the year for 2025, and explored through the year the past, present and future of the field, with articles on the origins of superconducting qubits1, the scaling of quantum computers2,3, and the success and failure of quantum computing start-ups4.

In line with our choice for technology of the year, 2025 was also designated by the United Nations as the International Year of Quantum Science and Technology, marking 100 years since the publication of a pivotal work from Werner Heisenberg5. And to cap it all, the Nobel Prize in Physics was awarded in October to John Clarke, Michel Devoret and John Martinis for work on quantum effects that underpin superconducting quantum computing.

Now in December, we return again to the IEDM and offer our highlights of the 2025 event. This year, the theme of the meeting is 100 years of field-effect transistors (FETs) and shaping the future of device innovations. As we discussed back in October6, it is 100 years since Julius Edgar Lilienfeld filed a patent for a FET. Such devices remain central to modern electronics and inevitably to the work reported at IEDM 2025, and the work we highlight here.

We begin with transistors made from two-dimensional (2D) materials, where Quentin Smets and colleagues at Imec, KU Leuven and Intel report approaches to integrate 2D FETs into back-end-of-line processes. The researchers introduce three distinct device integration schemes: damascene-type top contacts; replacement oxide technology; and interlayer removal. As Peigen Zhang and He Tian of Tsinghua University explain in a News & Views article about the work, these schemes provide “new structural options for back-end integration of 2D materials”.

Elsewhere at IEDM 2025 are advances with oxide-semiconductor channel transistors, where Mutsumi Okajima and colleagues at Kioxia Corporation report a 3D dynamic random-access memory (DRAM) architecture using such transistors. The approach, which provides a potential route to high-density, low-power memory, is discussed in a News & Views article by Taeyoung Song and Asif Khan of the Georgia Institute of Technology.

Also at the meeting, and using polycrystalline silicon thin-film transistors (TFTs), Sanghun Jeon and colleagues at the Korea Advanced Institute of Science and Technology (KAIST) report the development of a neuromorphic silicon retina that can perceive and process light as spikes. The approach involves the integration of the polycrystalline silicon TFTs, which function as spike generators, and amorphous silicon photodiodes. As Shaocong Wang and Yuchao Yang of Peking University explain in a News & Views article about the work, the silicon retina could be of use in the development of “low-power vision systems for edge robotics, autonomous navigation and wearable devices, where energy budgets are tightly constrained”.

There is then work from Jiandong Ye, Guoquan Lu, Yuhao Zhang and colleagues at the University of Hong Kong, Virginia Tech, the City University of Hong Kong and Nanjing University on the development of an ultrawide-bandgap (UWBG) power module that is capable of 1,000 V and 200 A switching. As Savannah Eisner of Columbia University discusses in a News & Views article about the study, the system is created by “co-optimizing the electrical, thermal and mechanical aspects of both the device and the package, a holistic approach that could set the template for how future UWBG systems are built”.

Elsewhere, we highlight a report on a monolithic complementary FET architecture that integrates n-type metal–oxide–semiconductor and p-type metal–oxide–semiconductor silicon transistors with distinct channel crystal orientations. We highlight work on a germanium-on-silicon single-photon avalanche diode pixel array that can be used to build sensors for outdoor applications, and work on a multi-mode microelectromechanical systems (MEMS) acoustic clock.

We also then highlight a report on a fully analogue in-memory Ising machine that uses complementary metal–oxide–semiconductor (CMOS)-integrated voltage-controlled magnetic tunnel junctions. Finally, we highlight advances in the monolithic 3D integration of capacitive memory on silicon CMOS chips, and advances in the development of gallium nitride chiplet technology.