Fig. 3: Floating-gate memories based on NbS2–MoS2 patterned heterostructures. | Nature Electronics

Fig. 3: Floating-gate memories based on NbS2–MoS2 patterned heterostructures.

From: Non-volatile memories based on patterned metal–semiconductor heterostructures of niobium disulfide and molybdenum disulfide

Fig. 3: Floating-gate memories based on NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.

a, Side-view schematic and optical micrograph of the floating-gate memory device based on NbS2–MoS2 patterned heterostructures. Scale bar, 10 μm. b, Transfer characteristics of the FGFETs fabricated with the NbS2–MoS2 heterostructure at room temperature. c, Output characteristics of the FGFETs after being programmed with different programming voltages. d, Time dependence of the device conductance for different levels of programming voltages. e, Linear evolution of the conductance values for potentiation and depression stages by applying voltage pulses to the gate. f, Two-state retention time at different temperatures. The drain–source conductance (Gds) is shown as a function of time. The red curve and blue curve show the data obtained at 300 K and 425 K, respectively. g, Floating-gate endurance test. The drain–source current (Ids) is shown as a function of the number of P/E cycles. Each P/E cycle consists of a 100-ms, +11.5-V pulse for the erase operation, and a 100-ms, −11.5-V pulse for the program operation. The device failed after 63,475 P/E cycles.

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