Main

In-memory computing could be used to meet the demand for high-performance and low-energy computation required by data-intensive applications1 such as machine learning2,3 and the Internet of Things4. The approach performs computing in the physical layer of memories through Kirchhoff’s and Ohm’s laws, thereby avoiding the bottlenecks of the traditional von Neumann architecture5,6. Various material systems have been explored for in-memory computing5,7,8,9. Among them, two-dimensional (2D) transition metal dichalcogenide (TMDC) semiconductors have attracted attention due to their atomic-scale thickness, layer-dependent band structure10 and favourable electrical properties11,12. In particular, monolayer molybdenum disulfide (MoS2) exhibits ideal semiconducting behaviour with a large direct bandgap of 1.8 eV (ref. 13) and a high on/off current ratio of 108 in n-type field-effect transistors (FETs)14. MoS2 has been used to fabricate various relatively large-scale electronic devices15,16,17,18,19. However, the performance is still limited by a large contact resistance with conventional electrode contacts20.

2D metal–semiconductor junctions based on TMDC heterostructures21 are a potential route to reduce contact resistance by mitigating Fermi level pinning and modulating the Schottky barrier22. Lateral and vertical TMDC heterostructures can be synthesized using chemical vapour deposition or metal–organic chemical vapour deposition (MOCVD), resulting in high-crystallinity growth and precise control over the number of layers23,24,25,26. However, these methods often face scalability challenges for integrated device design27. Alternative methods, such as sulfurization, enable large-area growth with high reproducibility but typically have low crystal quality and monolayer uniformity28,29,30,31. Developing effective 2D metal–semiconductor junctions depends on identifying a technique that balances high-quality growth with scalability and integration into devices. In addition, patterned heterostructures can allow for precise control over junction formation, carrier transport and local electronic properties. However, achieving high-resolution patterning without compromising material quality remains challenging.

In this Article, we report a versatile and scalable fabrication method that uses MOCVD and sulfurization to create patterned TMDC metal–semiconductor heterostructures with high growth quality and application flexibility. A monolayer TMDC (MoS2) is first grown by MOCVD, transferred to a substrate and etched into the desired pattern. Then, a 3-nm-thick layer of niobium is evaporated onto the sample and sulfurized to create 2D NbS2 contacts. The high quality and uniformity of the heterostructures are verified by atomic force microscopy (AFM) and Raman spectroscopy measurements. NbS2 reduces the contact resistance compared with pristine MoS2 FETs, leading to an up to ninefold increase in on current, an effective mobility of up to 77 cm2 V−1 s−1 and a 95.8% device yield across 144 FETs over a centimetre scale. Additionally, by using the heterostructures in floating-gate field-effect transistors (FGFETs), the devices exhibit a large programming window and the capability to precisely and continuously modulate conductance, with an endurance of over 60,000 programming pulses and an estimated retention time of approximately 19 years. Device simulations show that the large programming window (around 14 V) that can be obtained in long-channel devices is maintained as the gate length is reduced, with proper control oxide scaling, to 10 nm.

Production and characterization of patterned NbS2–MoS2 heterostructures

We synthesized NbS2–MoS2 patterned heterostructures via a two-step process involving MOCVD and sulfurization (Fig. 1a). First, monolayer MoS2 was grown on sapphire by MOCVD and transferred onto a Si/SiO2 substrate (Supplementary Fig. 1). Photolithography and dry etching were then used to define MoS2 channels, followed by Nb deposition and sulfurization to form NbS2 and heterostructures. This approach is generalizable for fabricating other TMDC heterostructures composed of a monolayer semiconductor and few-layer metallic contacts. Additional details on the production are available in the Methods.

Fig. 1: Fabrication and characterization of NbS2–MoS2 patterned heterostructures.
Fig. 1: Fabrication and characterization of NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.
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a, Schematic of the process flow for producing NbS2–MoS2 patterned heterostructures. b,c, AFM images and the corresponding height profile of NbS2 (b) and monolayer MoS2 (c) in the heterostructure. d,e, Raman spectra at room temperature for the NbS2 region and the MoS2 region before and after sulfurization on a Si/SiO2 substrate, respectively. f,g, Optical micrographs of NbS2–MoS2 patterns on a Si/SiO2 substrate. Scale bars, 50 µm. h, Raman intensity mapping collected from the region marked in f, with the pink colour indicating MoS2 and blue colour indicating NbS2. Scale bar, 4 µm. i, STEM image showing the interface between NbS2 and MoS2 in the heterostructure. Scale bar, 2 nm.

The quality of the as-grown NbS2 samples in the heterostructure was first examined. Figure 1b shows the AFM image of a NbS2 sample on a Si/SiO2 substrate after sulfurization, revealing a smooth surface with a thickness of 12 nm (approximately 17 layers). The Raman spectra shown in Fig. 1c display strong peaks at 339 cm−1 (E12g) and 380 cm−1 (A1g), consistent with the vibrational modes of 2H-phase NbS2 (refs. 32,33), confirming the high quality of sulfurized NbS2. Raman line scans collected from different regions of the sample, together with Raman mappings, are provided in Supplementary Figs. 6 and 7. Furthermore, Supplementary Fig. 2 presents the X-ray photoelectron spectroscopy (XPS) spectra (orange dots) with the corresponding fitting curves (blue and red lines) of the sulfurized NbS2 samples. The presence of distinct peaks for Nb4+ and Nb5+ states in the fitting curves verifies the formation of Nb4+ and Nb5+ chemical bonds during sulfurization. No metallic Nb signals are detected in the NbS2 samples, indicating complete sulfurization without residual Nb. The Nb5+ component observed in the XPS spectra originates mainly from near-surface oxidation, considering the limited XPS probing depth (~5–8 nm) relative to the ~12-nm NbS2 film thickness. The oxidized fraction is small (~10% within the XPS depth), and the film remains predominantly metallic NbS2 without observable degradation in its electrical conductivity, as supported by the electrical results discussed in the next section. Additional Raman and AFM characterization of sulfurized NbS2 at different temperatures is presented in Supplementary Figs. 3 and 4, providing insights into the as-grown quality of NbS2 films under varying sulfurization conditions.

To assess the quality of the MOCVD-grown monolayer MoS2 after sulfurization, Raman spectra, AFM and XPS analysis were also performed on the MoS2 region in the heterostructure. Figure 1d shows the Raman spectra obtained from the same MoS2 region before and after sulfurization. Both spectra exhibit sharp peaks at 383 cm−1 (E12g) and 402 cm−1 (A1g) with large overlap, confirming the post-sulfurization preservation of the integrity and quality of monolayer MoS2. Raman line scans collected from different regions of the sample, together with Raman mappings, are provided in Supplementary Figs. 6 and 8. XPS spectra with the corresponding fitting curves shown in Supplementary Fig. 5 detail the chemical states in MoS2. Within the detection limit of XPS, no distinct Nb-related signal is observed after sulfurization, whereas the weak spectral fluctuations and shoulder features can be attributed to minor surface oxidation and background contributions. Figure 1e presents the AFM image of monolayer MoS2 on a sapphire substrate, showing a smooth surface with a thickness of 0.7 nm, further validating the quality of the MoS2 layer.

Two typical optical micrographs of NbS2–MoS2 patterns are shown in Fig. 1f,g, demonstrating the flexible heterostructure design achieved by our two-step process. Figure 1h presents the Raman intensity mapping collected from the dashed line box region marked in Fig. 1f. The uniform signals across the individual material regions correspond to the characteristic modes of NbS2 and MoS2, respectively, indicating a consistent chemical distribution without alloying. The clear boundaries between the NbS2 and MoS2 regions further confirm the successful formation of the heterostructures. To investigate the atomic structure and interface of the heterostructure in more detail, aberration-corrected annular dark-field scanning transmission electron microscopy (STEM) imaging was performed, with the results displayed in Fig. 1i. The absence of visible defects in the individual regions suggests a high crystalline quality of the heterostructure samples. The few-layer NbS2 exhibits stronger contrast compared with the monolayer MoS2 due to its greater thickness. A clear and sharp interface between the two materials is observed, with NbS2 vertically stacked on top of the MoS2 lattice in a hexagonal arrangement, maintaining the same lattice structure and orientation.

Electrical transport of NbS2–MoS2 patterned heterostructures

2D metal–semiconductor junctions are anticipated to enhance the electrical properties of TMDC materials by using 2D contacts. To evaluate the electrical performance, FET devices were fabricated using NbS2–MoS2 patterned heterostructures. The structural schematic of a two-probe FET device and a typical optical microscopy image of an FET array are shown in Fig. 2a,b, respectively. The patterned heterostructure was produced on a Si/SiO2 substrate, as described previously, with the monolayer MoS2 functioning as the transistor channel, and NbS2 functioning as the 2D contact. The Si substrate is the back gate and SiO2 is the dielectric layer, whereas a Ti/Au stack is used as the source/drain electrodes connecting to NbS2. Voltage potential measurements from different probes on the device (Supplementary Fig. 9) reveal a negligible voltage drop across the NbS2 region compared with the MoS2 channel. Room-temperature I–V characterization of sulfurized NbS2 (Supplementary Fig. 10) shows a linear curve with a total resistance (Rtot) of 60 Ω µm. Furthermore, transfer length method analysis reveals that the NbS2–MoS2 heterojunction contact resistance (440 Ω μm) is one order lower than that of conventional MoS2–Ti/Au contacts (4.9 kΩ μm) (Supplementary Fig. 11), indicating a more efficient carrier injection. These results confirm the metallic behaviour of sulfurized NbS2, which primarily serves as a 2D contact for the MoS2 channel.

Fig. 2: FET devices based on NbS2–MoS2 patterned heterostructures.
Fig. 2: FET devices based on NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.
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a, Schematic side view of an FET device fabricated using NbS2–MoS2 patterned heterostructures. b, Photograph of a part of a fabricated FET array based on the patterned heterostructures on a Si/SiO2 substrate. c, Typical temperature dependence of the transfer characteristics (red plots) for NbS2–MoS2 patterned heterostructure FETs and room-temperature transfer characteristics for the FET devices based on pristine MoS2 (blue plot). Inset: optical micrograph of an FET device fabricated using NbS2–MoS2 patterned heterostructures. Scale bar, 20 μm. d, Temperature dependence of the conductance of NbS2–MoS2 patterned heterostructure FETs for different values of the gate voltage. The exponential temperature dependence suggests a thermally activated conductance. e, Transfer characteristics of 36 FETs with a 10-μm channel length from the area shown in b. f, Distribution of the on-state current of 144 FETs at Vds = 50 mV and Vg = 20 V. The white cells denote failed devices. g, Statistical distribution of mobility and subthreshold swing (SS) of the 144 FETs shown in f.

Figure 2c presents the gating characteristics, in the linear regime with Vds = 50 mV, of the transistor with 2D NbS2 contacts, as well as an MoS2 transistor with three-dimensional (3D) Ti/Au contacts for comparison. Both devices exhibit typical n-type channel behaviour, with the NbS2–MoS2 devices showing higher current than MoS2 devices with 3D Ti/Au contacts, with a relative increase up to nine times at Vg = 20 V and T = 300 K. Since the channel material is the same (MoS2), the higher current of the NbS2–MoS2 devices is attributed to reduced contact resistance. To investigate the channel and contact properties of NbS2–MoS2 devices, Fig. 2c also shows the drain–source current (Ids) in the heterostructures for different temperatures, from 300 K to 100 K, whereas Fig. 2d shows the relative device conductance Gd= Ids/Vds (circle symbols) as a function of temperature for different values of Vg. As evident from Fig. 2d, the device conductance Gd shows a clear thermal activation dependence of the form \({G}_{{\rm{d}}}={G}_{\infty }{{\rm{e}}}^{-{E}_{{\rm{a}}}/{kT}}\), where k is Boltzmann’s constant, \({G}_{\infty }\) is a pre-exponential factor, and with a thermal activation energy extrapolated to be Ea\(\,\approx \,\) 1 meV, showing only minor variation and no systematic dependence on Vg (Supplementary Fig. 12), which is much smaller than the effective experimental contact barrier (Supplementary Fig. 13) and the previously simulated Schottky barrier height24. Such dependence is observed for Vg in the range from 0 to 20 V, suggesting a negligible energy barrier height and channel-dominated transport at the contact for the NbS2–MoS2 devices. This behaviour is commonly associated with trap-assisted transport in MoS2 channels and does not diminish the clear advantage of the NbS2 contact, whereas further improvements through interface and dielectric engineering remain possible. In fact, contact barrier effects would be observable only at higher Vg with a conductance \({G}_{{\rm{d}}}\propto {T}^{\frac{3}{2}}{{\rm{e}}}^{-{\varnothing }_{{\rm{B}}}/{kT}}\), where ΦB is the contact energy barrier height. Thermal activation in conductance has been already reported for MoS2 devices34,35,36,37,38,39,40,41 and can be attributed to mobility or charge density activation. The thermal activation suggests a dominant role of traps in the electrical transport in the MoS2 channel37,42. The heterostructure FET exhibits an on/off ratio of 106 and a field-effect mobility of μFE ≈ 77 cm2 V−1 s−1 at the maximum tested gate voltage (20 V). Owing to improved contacts, both on/off ratio and field-effect mobility of the heterostructure FET using 2D NbS2 contact with MoS2 surpass those of pristine MoS2 FET with 3D Ti/Au contacts (105 and 5.8 cm2 V−1 s−1, respectively), with representative gating and biasing curves shown in Supplementary Fig. 14.

Our NbS2–MoS2 patterned heterostructures facilitate the batch fabrication of FET arrays on scales ranging from centimetres to full wafers (Fig. 2b). The gating characteristic curves and on-state current distribution for 144 FETs with a 10-μm channel length over a 5 × 4-mm2 area are shown in Fig. 2e,f. Owing to the good uniformity of the MOCVD-grown MoS2 film and the reliable connection provided by the 2D NbS2 contact, we achieved a device yield of 95.8% and a 17.4% variation in on-state current (defined as σIon/〈Ion〉, where σIon and 〈Ion〉 are the standard deviation and mean value of Ion, respectively) across the centimetre range. Additionally, a statistical analysis of the field-effect mobility and subthreshold swing for the 144 FETs revealed a Gaussian distribution in both parameters (Fig. 2g). The average field-effect mobility is 45.6 cm2 V−1 s−1, with the maximum reaching 60 cm2 V−1 s−1. The variations in mobility and subthreshold swing are 16.6% and 12.7%, respectively, which are comparable with the variability observed in devices fabricated using chemical-vapour-deposition-grown pristine MoS2 films43,44. This suggests that the variations are mainly generated during the transfer and fabrication processes, rather than originating from the material itself. The overall device performance ranks among the highest for monolayer MoS2 transistors (Supplementary Table 1), highlighting the ability of our NbS2–MoS2 heterostructures to achieve high performance and maintain good uniformity.

It should be noted that a van der Waals (vdW) gap may, in principle, exist at the NbS2–MoS2 metal–semiconductor interface, which could influence carrier injection. However, our NbS2–MoS2 heterostructure is formed via a sulfurization-induced phase conversion process rather than by mechanical transfer or stacking, which is expected to promote an intimate interfacial coupling and suppress the formation of a large vdW gap. Although the direct structural characterization of the vdW gap is not available at this stage, the observed low contact resistance, near-ohmic output behaviour and excellent device uniformity across centimetre-scale areas indicate efficient electronic coupling at the NbS2–MoS2 interface, suggesting that any residual vdW gap, if present, does not dominate the contact performance.

Non-volatile memories based on NbS2–MoS2 patterned heterostructures

We demonstrate non-volatile memories based on our NbS2–MoS2 patterned heterostructures by using FGFETs. The side-view schematic and optical micrograph of the FGFET structure are shown in Fig. 3a. Similar to the FET devices, monolayer MoS2 and sulfurized NbS2 serve as the transistor channel and 2D contact, respectively, with a Si substrate functioning as the back gate. The key difference is the introduction of a 5-nm-thick Pt layer as the floating gate, positioned between the blocking and tunnel oxides (270 nm and 7 nm thick, respectively) composed of SiO2. This floating gate, as reported in our previous work7, can be utilized to store charge and realize non-volatile memory functionality. Although the introduction of a Pt floating gate adds additional fabrication steps, it provides a well-defined work function, good chemical stability and enables precise electrostatic control at the nanoscale, which are advantageous for reliable charge storage and device scaling in atomically thin 2D FGFETs.

Fig. 3: Floating-gate memories based on NbS2–MoS2 patterned heterostructures.
Fig. 3: Floating-gate memories based on NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.
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a, Side-view schematic and optical micrograph of the floating-gate memory device based on NbS2–MoS2 patterned heterostructures. Scale bar, 10 μm. b, Transfer characteristics of the FGFETs fabricated with the NbS2–MoS2 heterostructure at room temperature. c, Output characteristics of the FGFETs after being programmed with different programming voltages. d, Time dependence of the device conductance for different levels of programming voltages. e, Linear evolution of the conductance values for potentiation and depression stages by applying voltage pulses to the gate. f, Two-state retention time at different temperatures. The drain–source conductance (Gds) is shown as a function of time. The red curve and blue curve show the data obtained at 300 K and 425 K, respectively. g, Floating-gate endurance test. The drain–source current (Ids) is shown as a function of the number of P/E cycles. Each P/E cycle consists of a 100-ms, +11.5-V pulse for the erase operation, and a 100-ms, −11.5-V pulse for the program operation. The device failed after 63,475 P/E cycles.

The room-temperature gating characteristic of our memory device based on the NbS2–MoS2 heterostructure is presented in Fig. 3b, with a comparison available in Supplementary Fig. 15 showing the transport behaviour of pristine MoS2. A memory window of 13.8 V can be estimated from the total shift of the memory threshold voltage in our NbS2–MoS2 sample, which is slightly larger than that of pristine MoS2 (12 V). In particular, the heterostructure shows an on/off ratio of 107, two orders of magnitude higher than that of pristine MoS2. This improvement is attributed to the lower contact resistance and Schottky barrier height. Although the memory window remains comparable, the enhanced on/off ratio enabled by the NbS2 contact is expected to improve the read-out margin, suppress leakage current and enhance the signal reliability of the memory operation. Supplementary Fig. 16 presents additional gating characteristics of the floating-gate memory device based on the NbS2–MoS2 heterostructure under varying sweeping rates and temperatures. As shown in Supplementary Fig. 16a, higher sweeping rates result in a narrower memory window and maintain a similar on-state current, as the reduced sweep duration limits the time available for complete charge trapping and detrapping. In Supplementary Fig. 16b, a reduction in temperature from 300 K to 10 K leads to both a lower on-state current (according to what is observed for transistors in Fig. 2b) and a narrower memory window (attributed to slower charge transfer processes at lower temperatures), which hinder effective charge storage. These findings confirm that the floating-gate memory behaviour is governed by the amount of charge stored in the charge trap layer.

To read the memory state of the device, a constant voltage (Vg(read)) was applied to the gate and the drain–source current was measured after programming with different gate biases. The output characteristics (Fig. 3c) exhibit linear behaviour, suggesting ohmic-like contacts, in agreement with the negligible barrier found for transistors. Figure 3d shows the normalized conductance over time for various programming voltages, demonstrating the ability to set and maintain different channel conductance levels, with stability observed over a 1-h period. Additionally, by applying short potentiative and depressive pulses, we can finely tune the conductance states of the device to desired levels. Figure 3e illustrates the conductance changes in the memory device as a function of the number of applied pulses. When potentiative pulses (−10-V amplitude, 10-ms duration, 1-s rest time) were applied to the gate, we achieved linear control over the conductance. Conversely, the device was reset by applying depressive pulses (+10-V amplitude, 10-ms duration, 1-s rest time). This precise modulation of conductance underscores the robustness and reliability of our memory device for potential applications in multilevel data storage. The ability to achieve fine control over the conductance with consistent and repeatable pulses highlights the effectiveness of our NbS2–MoS2 patterned heterostructures in enhancing memory device performance.

To examine the data storage capability of our floating-gate memory devices, we first recorded the drain–source conductance (Gsd) versus time at room temperature with Vg(read) = 0 V after programming with Vg(program) = 12.5 V and Vg(program) = –12.5 V, respectively (Fig. 3f, red curves). The conductance remained stable over a period of 10 h without any data loss, indicating strong data storage capability. Additionally, we tested our sample at an elevated temperature of 425 K to calculate the equivalent retention time at room temperature using the Arrhenius model:

$${A}_{{\rm{f}}}=\exp \left[\frac{{E}_{{\rm{a}}}}{k}\left(\frac{1}{{T}_{{\rm{n}}}}-\frac{1}{{T}_{{\rm{e}}}}\right)\right],$$

where Af is the acceleration factor, Ea is the activation energy (a typical activation energy is 0.8 eV for effects related to charge loss when no voltage is applied to the device), Tn is the temperature of the normal environment and Te is the elevated temperature. As demonstrated by the blue curves in Fig. 3f, the conductance exhibits a faster degradation rate at high temperature, according to the higher erasing observed in the sweep characteristics in Supplementary Fig. 16b, but the data can still be stored for over 18.2 h. Using the Arrhenius model, we calculated an acceleration factor of 8,973, which indicates that if the data persists for 18.2 h at 425 K, it will last 8,973 times longer at 300 K. This corresponds to an equivalent retention time at room temperature of approximately 19 years. A sensitivity analysis of the projected retention time using different assumed activation energies (for example, 0.7 eV and 0.9 eV) shows that the retention time remains in the multiyear regime over this experimentally reasonable range. Furthermore, an endurance test was conducted on our memory device to assess its reprogrammability (Fig. 3g). The drain–source current (Ids) was measured as a function of the number of program/erase (P/E) cycles. Each P/E cycle consisted of a 100-ms pulse of +11.5 V for the erasing operation and a 100-ms pulse of –11.5 V for the program operation. The endurance results indicate that our memory devices can sustain more than 60,000 programming pulses before failure, demonstrating robust non-volatile performance. The device maintained stable current levels during the cycling process, which underscores its potential for long-term data storage and repeated reprogramming.

Simulation results based on NbS2–MoS2 patterned heterostructures

2D device simulations were performed by Synopsys technology computer-aided design (TCAD)45 to fit the experimental measurements on the long-channel device with the aim to investigate the scaling potential for circuit applications. Longitudinal transport is modelled through the conventional drift–diffusion model with Fermi–Dirac statistics and Shockley–Read–Hall recombination. Interface semiconductor bandgap traps are included in the simulation model to reproduce the low current–voltage slope and the large current observed at 0 V (ref. 46). In agreement with the experimental measurements on transistors, contacts are treated as ideal. Charge injection into and from the floating gate is responsible for the observed memory window and is modelled by a non-local (based on Wentzel–Kramers–Brillouin) oxide-trap-assisted electron tunnelling across the tunnel oxide. Hole tunnelling is not considered due to the expected high band offset.

Figure 4 shows the hysteresis cycle for the measured (black symbols) and simulated (black line) long-channel device with L = 5 μm. As observed from both log view (panel a) and linear view (panel b), a good agreement is obtained in a large current range of five decades with numerical simulation. Figure 4a,b also shows the simulated (solid lines) scaled drain current of the hysteresis cycles at different gate lengths (L), from the long channel to a short channel of 10 nm. Figure 4c shows the programming window, extracted at a constant current (Ids) × L/W = 1 nA, as a function of L and for different values of the control oxide thickness (tcg). Figure 4c shows that the large programming window of the long channel, at nominal tcg = 270 nm, is maintained down to a gate length of L = 100 nm, whereas it collapses for shorter gate lengths due to poor device electrostatics. However, reducing the control oxide thickness to tcg = 40 nm enables us to obtain a programming window of 13 V for FGFETs with gate lengths of only 10 nm. Although the present study is conducted at the micrometre scale, the TCAD predictions based on the experimentally validated devices suggest that further scaling towards submicrometre and ~100-nm-channel-length FGFETs remains feasible for future research.

Fig. 4: Simulated scaling behaviour of floating-gate memories based on NbS2–MoS2 patterned heterostructures.
Fig. 4: Simulated scaling behaviour of floating-gate memories based on NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.
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a,b, Simulated hysteresis cycles shown in the log scale (a) and linear scale (b) as the gate length (L) is scaled from 5 μm to 10 nm. c, Programming window extracted from the hysteresis cycles at a constant drain current density of Ids × (L/W) = 1 nA for different values of the control oxide thickness (tcg).

Conclusions

We have reported a scalable method for synthesizing 2D TMDC heterostructures with high quality, uniformity and flexible pattern designs, which offers a promising route for the mass production of 2D electronic devices. Our 2D metal–semiconductor heterojunctions are particularly promising for the development of low-power devices due to the reduction in energy consumption achieved through the lowering of contact resistance. Moreover, we use the heterostructures to create non-volatile memory devices with excellent programming capabilities, robust data storage performance and promising potential for scaling the gate length down to 10 nm. Unlike 3D NAND flash memory, which relies on vertical stacking to achieve a high storage density, our atomically thin NbS2–MoS2 memory platform could enable planar integration with logic devices and combined transistor and memory functionality for low-power heterogeneous and in-memory computing systems. This work highlights the critical role of advanced material design in achieving the required scalability and performance for future low-energy electronic applications.

Methods

MoS2 film synthesis

To synthesize the MoS2 film, a two-inch c-plane sapphire wafer was first annealed in air for 6 h to achieve an atomically smooth surface. After annealing, the substrate was treated with a 10 wt% of potassium hydroxide solution and then cleaned with deionized water. A mixture solution containing 0.1 mol l−1 of sodium chloride and 0.015 mol l−1 of sodium molybdate was spin coated onto the sapphire substrate. Sodium chloride was used to accelerate the growth and decrease the nucleation density, whereas sodium molybdate served as the Mo precursor in the initial stage. The substrate was then loaded into the centre of a quartz tube inside a furnace. During the growth process, molybdenum hexacarbonyl and diethyl sulfide were introduced into the quartz tube as precursors, carried by argon gas at flow rates of 10 s.c.c.m. and 3 s.c.c.m., respectively. The precursors were stored in a bubbler maintained at 25 °C. A small amount of hydrogen (H2) and oxygen (O2) were separately delivered into the growth chamber to balance the growth rate by etching and achieve a monolayer. The MoS2 growth was conducted for 30 min at 870 °C and atmospheric pressure, after which the precursor supply was abruptly cut off. Finally, the furnace was allowed to cool naturally to room temperature, with an argon gas flow of 210 s.c.c.m. maintained from the beginning to the end of the process.

Sample transfer

To transfer the MOCVD-grown monolayer MoS2 from the sapphire substrate, the sample was first spin coated with poly(methyl methacrylate) (PMMA) A2 at a speed of 2,000 rpm for 1 min. It was then baked on a hotplate at 70 °C for 15 min to dry. The edges of the PMMA layer were carefully scratched with a sharp tweezer, after which the sample was covered with a thermal release tape and immersed in water for 15 min. This process allowed the PMMA layer, along with the MoS2 film, to detach from the sapphire substrate and can then be transferred onto a Si/SiO2 substrate. To enhance adhesion, the sample was baked again on a hotplate at 55 °C for 1 h. The thermal release tape was then removed by increasing the baking temperature to 135 °C. Finally, the sample was immersed in acetone overnight to remove the PMMA layer and then annealed in a high vacuum at 250 °C for 6 h to eliminate any PMMA residue.

Patterned heterostructure production

First, the MoS2 film was transferred onto a Si/SiO2 substrate, as described in the ‘Sample transfer’ section. It was then etched into the desired geometry using photolithography techniques, using LOR 5A and AZ 1512 HS as photoresist layers, and a xenon difluoride chemical etcher. The photoresist layers were removed by immersing the sample in dimethyl sulfoxide overnight. Subsequently, photolithography was applied again to create Nb patterns, and a 3-nm-thick layer of Nb was evaporated onto the sample in preparation for NbS2 growth. The sample was then sulfurized in a quartz tube at 400 °C for 1 h, with a H2S flow rate of 30 s.c.c.m. and an Ar flow rate of 100 s.c.c.m. To minimize unintentional oxidation, the sulfurized NbS2 samples were stored and transferred in an inert glovebox environment between fabrication steps whenever possible.

Raman measurements

Raman measurements were conducted using a Renishaw inVia confocal Raman microscope at room temperature. A 532-nm-wavelength laser with a power of 1 mW was used to excite the samples. A diffraction grating (3,000 gratings mm−1) was used to achieve suitable spectral ranges and resolution.

STEM measurements

STEM experiments were performed using a double aberration-corrected FEI Titan Themis microscope, operating at an acceleration voltage of 80 kV. The STEM images were captured with a probe convergence angle of 20 mrad and a camera length of 185 mm, corresponding to the high-angle annular dark-field detector with a collection angle of 49.5–198.0 mrad. The estimated probe current was approximately 16–20 pA. Images were recorded at a resolution of 512 × 512 pixel2 with an 8-µs dwell time. The resulting images were further processed using bandpass and inverse fast Fourier transform filtering in ImageJ47.

Device fabrication

The FET devices were fabricated by depositing electrode contacts on top of NbS2 in patterned heterostructures on Si/SiO2 substrates. Initially, laser writer lithography was used to create electrode patterns using LOR 5A and AZ 1512 HS as photoresist layers. Subsequently, a 2-nm/80-nm-thick layer of Ti/Au was deposited as electrodes using an electron-beam evaporator (LAB 600H). Finally, a lift-off process was performed in dimethyl sulfoxide to remove the photoresist layers.

The FGFET devices were fabricated by depositing electrode contacts using the same method as described for the FET devices, following the production of the heterostructures on a Si/SiO2 substrate with a prepared floating gate. The floating gate was created by depositing a 5-nm-thick layer of Pt on a Si/SiO2 substrate using photolithography (with LOR 5A and AZ 1512 HS as photoresist layers). A 7-nm-thick SiO2 blocking oxide layer was subsequently grown by thermal atomic layer deposition using t-butylamino silane and water as precursors.

Transport measurements and memory characterization

Electrical transport measurements were conducted in a Janis closed-cycle cryogen-free cryostat. Before measurements, the sample was annealed in a high vacuum at 120 °C for 6 h to remove any absorbed oxygen and humidity from the surface of the 2D materials. Two-probe d.c. electrical measurements were performed using an Agilent E5270B source meter by applying d.c. source–drain voltage and back-gate voltage. Hysteresis characterizations and pulse programming were conducted with an Agilent E5270B mainframe, equipped with E5287A-ATO and E5281B-FG modules.

Device simulations

Device simulations were performed using Synopsys TCAD 44 to match the experimental measurements of long-channel devices and assess the scaling potential for circuit applications. The simulations used a conventional drift–diffusion model with Fermi–Dirac statistics and Shockley–Read–Hall recombination to describe longitudinal transport, incorporating interface semiconductor bandgap traps to capture the low current–voltage slope and large current observed at zero bias. Charge injection into and from the floating gate was modelled using a non-local, oxide-trap-assisted electron tunnelling mechanism based on the Wentzel–Kramers–Brillouin approximation. The programming window was analysed as a function of gate length and control oxide thickness, utilizing numerical extraction techniques to evaluate scaling trends.