Fig. 4: Simulated scaling behaviour of floating-gate memories based on NbS2–MoS2 patterned heterostructures. | Nature Electronics

Fig. 4: Simulated scaling behaviour of floating-gate memories based on NbS2–MoS2 patterned heterostructures.

From: Non-volatile memories based on patterned metal–semiconductor heterostructures of niobium disulfide and molybdenum disulfide

Fig. 4: Simulated scaling behaviour of floating-gate memories based on NbS2–MoS2 patterned heterostructures.The alternative text for this image may have been generated using AI.

a,b, Simulated hysteresis cycles shown in the log scale (a) and linear scale (b) as the gate length (L) is scaled from 5 μm to 10 nm. c, Programming window extracted from the hysteresis cycles at a constant drain current density of Ids × (L/W) = 1 nA for different values of the control oxide thickness (tcg).

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