Fig. 3: Weighted spin torque nano-oscillators (WSTNO) schematics. | Communications Engineering

Fig. 3: Weighted spin torque nano-oscillators (WSTNO) schematics.

From: Weighted spin torque nano-oscillator system for neuromorphic computing

Fig. 3

a WSTNO consisting of two magnetic memories (MRAM) as weights and a larger nanopillar as a spin torque nano-oscillator (STNO). The MRAMs are the non-volatile weights and the STNO is responsible for the non-linear transfer function of the neuron. b Schematic of the DC circuit used in the demonstration presented here. The input voltages (V1 and V2) are weighted by the MRAMs together with the bias current (IBias) and excite the STNO. The STNO excitation current (ISTNO) is converted non-linearly into an oscillating output power. c Example schematic showing the layout of two layers with each 3 inputs and 3 outputs demonstrating the scaling of the suggested neuromorphic circuit consisting of a crossbar array of MRAMs and STNO elements at the output of each layer. The number of inputs, outputs and layers can be scaled and each should increase the footprint linearly. The peak detector shown here is the interface circuit between layers and could be implemented in CMOS as discussed in the manuscript. d Network representation of the suggested neuromorphic circuit. Shown are the input voltages (Vi), the conductance as the weights (Gik) of the synapses (MRAMs), the neuron (STNO) with output power (Pk), the peak detector and the simplified subsequent layer.

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