Fig. 5: Simulation of stacked 16 Ge0.95Si0.05 nanowire FETs.
From: Fabrication and performance of highly stacked GeSi nanowire field effect transistors
a Schematic of simulated device structure. b Simulated current vs channel number. The S/D doping of 1.3 × 1019 cm−3 (magenta bars), 2 × 1020 cm−3 (olive bars), and 2 × 1020 cm−3 with warp around contacts (orange bars) are used. c Schematic of wrap around contact structure at S/D region. d Total parasitic capacitance (Cpar) consisting of shared Cpar (orange) and Cpar proportional to floor# (purple) with the floor# of 2/4/8/16. e Total gate capacitance (Cgg, olive line), Cpar (orange line), intrinsic gate capacitance (Cox, blue line) per floor and f intrinsic gate delay (olive)/gate delay (red) improvement vs floor# using the average WCH = 16 nm and HCH = 13 nm. The current difference between top channel and bottom channel is only 3.5% for the S/D doping of 2 × 1020 cm−3 with wrap around contacts. The effective dielectric constant (κeff = 15) the average of 5 nm Si3N4 inner spacer (κ = 7.2), 1 nm Al2O3 (κ = 9), and 9 nm ZrO2 (κ = 46).
