Table 1 Benchmarking of electrical performance metrics in 2D ferroelectric devices based on In2Se3
From: Indium selenides for next-generation low-power computing devices
Material | Device type | Contact metals | Channel thickness | Switching speed | On/off ratio | Memory window (V nm–1) | Retention time (s) | Endurance (cycles) | Ref. |
|---|---|---|---|---|---|---|---|---|---|
α-In2Se3 | Lateral gate FeFET | Ti/Au | 68 nm | NA | 104 | 0.39 | 3 × 104 | 105 | |
FeSFET | Cr/Au | Few layers | NA | 103 | NA | 104 | 104 | ||
– | 40 nm | 40 ns | 105 | 0.15 | 103 | 500 | |||
Ti/Pt | 47 nm | 1 s | 103 | 0.27 | 6 × 104 | 1,200 | |||
Ti/Au | 20–50 nm | 100 ns | 105 | 0.4 | 150 | 250 | |||
Ni | 30 nm | NA | 106 | NA | 0.1 | 104 | |||
FSJ | MoS2 or Ti | 12 nm | NA | 104 | NA | 5 × 103 | 4 × 103 | ||
Au or Ti | 40 nm | 10 ns | 103 | NA | 5 × 103 | 100 | |||
Au or WTe2 | 26 nm | NA | 105 | 0.17 | NA | NA | |||
CuInP2S6 (CIPS) | FTJ | Au/Cr | 4 nm | 10–50 μs | 107 | 0.14 | 107 | 5 × 103 | |
MoS2 with scandium-doped AlN (AlScN) gate | FeFET | Ti/Au | Few layers | NA | 106 | 0.3 | 105 | 104 |
