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Showing 1–10 of 10 results
Advanced filters: Author: Likuan Ma Clear advanced filters

  • Vertical transistors based on 2D semiconductors have the potential to reduce the footprint of electronic circuits, but their high-density integration remains challenging. Here, the authors report a vertical lamination approach for realizing high-density MoS2 vertical sidewall transistors.

    • Quanyang Tao
    • Ruixia Wu
    • Yuan Liu
    ResearchOpen Access
    Nature Communications
    Volume: 15, P: 1-7

  • Guan et al. report a simple yet multifunctional molecule which enables direct, photoresist-free patterning of quantum dots under ambient conditions. This advance leads to over 20% efficiency for patterned QLEDs and full-color active-matrix displays, offering a practical route to next-generation display manufacturing.

    • Jie Guan
    • Jianhang Ma
    • Yuanyuan Wang
    ResearchOpen Access
    Nature Communications
    Volume: 16, P: 1-13

  • The simultaneous scaling down of the channel length and gate length of 2D transistors remains challenging. Here, the authors report a self-alignment process to fabricate vertical MoS2 transistors with sub-1 nm gate length and sub−50 nm channel length, exhibiting on-off ratios over 105 and on-state currents of 250 μA/μm at 4 V bias.

    • Liting Liu
    • Yang Chen
    • Yuan Liu
    ResearchOpen Access
    Nature Communications
    Volume: 15, P: 1-7

  • The surface localized charges in colloidal quantum dots induce a degradation that limits the electroluminescence performance. Here, Chen et al. propose quantum dots with monmonotonically-graded core/shell/shell structures to boost the device’s performance by reducing the surface-bulk coupling.

    • Xingtong Chen
    • Xiongfeng Lin
    • Song Chen
    ResearchOpen Access
    Nature Communications
    Volume: 14, P: 1-9

  • Vertical field-effect transistors (VFETs) have potential for the realization of ultra-scaled devices, but their fabrication is usually limited by trade-offs between scalability and channel length. Here, the authors report a large-scale transfer method to realize indium gallium zinc oxide/graphene VFETs with van der Waals metallic contacts and reduced channel length.

    • Xiaokun Yang
    • Rui He
    • Yuan Liu
    ResearchOpen Access
    Nature Communications
    Volume: 15, P: 1-8

  • We develop a low-temperature, damage-free process using van der Waals lamination to integrate multiple circuit tiers into a monolithic three-dimensional device, incorporating unique multi-tier functionality and resolving legacy issues with the layering technology.

    • Donglin Lu
    • Yang Chen
    • Yuan Liu
    Research
    Nature
    Volume: 630, P: 340-345

  • Laminated van der Waals (vdW) metallic electrodes can improve the contact of 2D electronic devices, but their scalability is usually limited by the transfer process. Here, the authors report a strategy to deposit vdW contacts onto various 2D and 3D semiconductors at the wafer scale.

    • Lingan Kong
    • Ruixia Wu
    • Yuan Liu
    ResearchOpen Access
    Nature Communications
    Volume: 14, P: 1-8

  • The integration of high-κ dielectric layers with 2D semiconductors is essential for electronic applications, but remains challenging. Here the authors report a dry transfer method of wafer-scale Al2O3 and HfO2 thin films for the realization of top-gated monolayer MoS2 transistors and logic gates.

    • Zheyi Lu
    • Yang Chen
    • Yuan Liu
    ResearchOpen Access
    Nature Communications
    Volume: 14, P: 1-8