Engineering the future of 2D transistors: scaling, p-doping, and contact strategies

The integration of high-κ dielectrics with low equivalent oxide thickness (EOT) is crucial for the development of 2D transistors. Here, the authors report the low-temperature fabrication of wafer-scale HfO₂ dielectric films with sub-5-Å EOT and their application for the realization of high-performance 2D MoS₂ transistors and circuits.

2D semiconductors hold promise for the fabrication of high-density flexible integrated circuits, but they often require high-temperature processing or transfer steps. Here, the authors report the low-temperature ( ≤ 150 °C) fabrication of wafer-scale 3Dintegrated flexible complementary circuits based on 2D semiconductor inks.

Gate-all-around (GAA) nanosheet field-effect transistors (FETs) based on 2D semiconductors hold promise to complement silicon in future integrated circuits. Here, the authors report the wafer-scale growth of high-κ dielectric/semiconductor β-Bi₂SeO₅/Bi₂O₂Se/α-Bi₂SeO₅ heterostructures and their application for high performance 2D GAA FETs.

The integration of high-κ dielectric materials with 2D semiconductors remains an important challenge for the implementation of post-silicon 2D electronics. Here, the authors report a HfSe₂ plasma oxidation method to integrate HfO₂ dielectric layers on both n- and p-type 2D semiconducting channels, showing the realisation of high-performance complementary electronic devices.

The technological applicability of 2D semiconductor thin films is normally limited by the trade-off between their synthesis temperature and electrical performance. Here, the authors report a low-temperature polymer-free solution-based method to deposit high-mobility wafer-scale MoS₂ thin films, showing large-scale logic circuits and heterogeneous device integration.

2D semiconductors hold promise for solution-processed circuits requiring low-cost components and manufacturing scalability. Here, the authors investigate the criteria for the electrochemical exfoliation of high aspect-ratio nanosheets from 28 different layered materials, identifying the most promising candidates and key bottlenecks for solution-processed complementary electronics and functional circuits.

The integration of 2D semiconductors with high-κ dielectrics is an important requirement for the development of post-silicon electronics. Here, the authors report the thickness-controlled growth of MoO₃ nanoflakes with equivalent oxide thickness down to 0.9 nm, and their application for the realization of 2D electronic devices.

Flexible integrated circuits (ICs) based on 2D semiconductors hold promise for various applications, but their scale has so far remained limited to a low number of devices. Here, the authors report the fabrication of medium-scale flexible ICs integrating both combinational and sequential elements based on 2D MoS₂ transistors.

Vertical transistors based on 2D semiconductors have the potential to reduce the footprint of electronic circuits, but their high-density integration remains challenging. Here, the authors report a vertical lamination approach for realizing high-density MoS₂ vertical sidewall transistors.

Here, the authors report the ledge-guided epitaxial growth of high-density 2D Bi₂O₂Se fin arrays and their application for the realization of 2D multi-channel fin field-effect transistors, showing improved on-state currents as the number of integrated channels is increased.

The simultaneous scaling down of the channel length and gate length of 2D transistors remains challenging. Here, the authors report a self-alignment process to fabricate vertical MoS₂ transistors with sub-1 nm gate length and sub−50 nm channel length, exhibiting on-off ratios over 10⁵ and on-state currents of 250 μA/μm at 4 V bias.

Fufei An and colleagues report a solution-based strategy to prepare large-area, freestanding amorphous quasi-2D carbon nanomembranes from coal-derived carbon dots. Their mechanical and dielectric properties make these attractive materials for applications in nanoelectronic devices such as memristors and 2D-based transistors.

2D semiconductors have been proposed as a potential option to replace or complement silicon electronics at the nanoscale. Here, the authors discuss the recent progress and remaining challenges that need to be addressed by the academic and industrial research communities towards the commercialization of 2D transistors.

The application of 2D MoS₂ flexible integrated circuits (ICs) is currently limited by the material quality over large areas and the device fabrication technology. Here the authors report a gate-first fabrication technique to realize wafer-scale monolayer MoS₂ ICs on rigid and flexible substrates with high performance and low power consumption.

The current unbalance between the performance of n-type and p-type 2D transistors limits their applications for next-generation electronics. Here, the authors report the realization of high-performance 2D MoTe₂ p-type transistors by depositing metallic tellurium contacts via thermal evaporation.

The fabrication of ohmic electrical contacts for 2D semiconductor devices remains an important challenge towards their industrialization. Here, the authors report the low-temperature van der Waals epitaxial growth of ultrathin Cd electrodes for 2D MoS₂ transistors, showing improved contact resistance and mobility.

Laminated van der Waals (vdW) metallic electrodes can improve the contact of 2D electronic devices, but their scalability is usually limited by the transfer process. Here, the authors report a strategy to deposit vdW contacts onto various 2D and 3D semiconductors at the wafer scale.

2D semiconductors are attracting increasing attention as potentially scalable channels for future transistors, but the scaling of their contact length remains challenging. Here, the authors report the realization of 1D semimetal-2D semiconductor contacts based on individual carbon nanotubes with contact length down to 2 nm.

Edge-to-edge metal-semiconductor junctions have the potential to improve the performance of 2D transistors. Here, the authors report a synthetic strategy to fabricate monolayer MoS₂-PtTe₂ heterojunction arrays with sub-1-nm transfer length and enhanced carrier injection compared to vertical 3D metallic contacts.

The performance of p-type transistors based on 2D semiconductors has not yet reached the level required for the realization of competitive complementary metal-oxide-semiconductor (CMOS) circuits. In this Comment, the authors discuss the recent developments, current challenges, and future outlook of 2D p-type transistors.

2D p-type transistors are essential for the realization of complementary circuits for post-silicon electronics. Here, the authors report a chloroform doping strategy to fabricate p-type monolayer WSe₂ transistors with high performance and long-term stability.

2D semiconductors are attracting attention as a potential alternative for post-silicon electronics, but the fabrication of high-performance 2D p-type transistors remains a challenge. Here, the authors report the realization of bilayer WSe₂ p-type transistor arrays with on-state currents up to 421 μA/μm, on/off ratios exceeding 10⁷ and subthreshold swings as low as 75 mV/decade.

2D semiconductors are promising candidates for next-generation electronics, but the realization of competitive 2D p-type transistors remains challenging. Here, the authors report the characterization of nitric-oxide-doped monolayer and bilayer WSe₂ p-type transistor arrays, showing on-state currents up to 300–448 μA/μm, contact resistance down to 390–875 Ω·μm and on/off ratios of ~ 10⁶−10⁹.

The fabrication of n- and p-type semiconducting channels based on the same layered material would simplify the implementation of 2D electronics. Here, the authors report a spatially selective doping method for the synthesis of wafer-scale p- and n-type 2H-MoTe₂ thin films, and their application for the realization of complementary 2D transistor and inverter arrays.

The fabrication of high-performance p-type 2D transistors is still challenging. Here, the authors report the realization of wafer-scale p-type 2H-MoTe₂ transistor arrays contacted by Fermi-level tuned semimetallic 1T’-MoTe₂ electrodes, leading to improved contact resistance and device performance.