Fig. 1: The scenario and hardware architecture of the RePACK-based Compute-in-memory chip. | Nature Communications

Fig. 1: The scenario and hardware architecture of the RePACK-based Compute-in-memory chip.

From: Physical unclonable in-memory computing for simultaneous protecting private data and deep learning models

Fig. 1

a The application scenario of RePACK-based edge devices. In this scenario, the foundry provides the chips with identical designs. The edge device developer receives the chips and loads AI models to the chips with the RePACK scheme. The RePACK makes every chip a unique chip and gives these chips resilience against attack. b The attack model and the protections against these attacks include layer encryption, weight encryption, and input encryption. c An example of the encryption in this work. An original input is encrypted before sending it to the CIM module. The encrypted data successfully hides its details which are crucial to the user’s privacy. d The hardware architecture of the edge AI processor is based on the RePACK scheme. The CIM tiles include CIM cores, a TRNG core, and a PUF core. These cores are all made of 1T1R ReRAM array. This reduces the cost of design and fabrication and also provides reconfigurability.

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