Fig. 1: Scalable passive crossbar circuit design and fabrication.
a–e Schematics of fabrication steps. f Magnified schematic of a Pt/Ti/TiO2/Al2O3/Pt/Ti memristor at a certain crosspoint in panel (e) (red dotted line). g. A top-view optical image of multiple 32 × 32 passive crossbar circuits fabricated on a 4-inch wafer. h–j Top-view SEM images of a representative 32 × 32 passive crossbar circuit (h), along with magnified views of a 3 × 3 sub-array (i) and a 1 × 1 sub-array (j). The device line width is 2 μm. The scale bar for (h–j) is 100 μm, 10 μm, and 2 μm, respectively. k Cross-sectional high-resolution TEM image of junction structure at the crosspoint. The scale bar is 5 nm. l A top-view optical image of the hardware measurement system with the fabricated passive crossbar circuits (inset). The crossbar circuit is wire-bonded and mounted on the board system. The scale bar is 30 mm and 3 mm (inset). m Histograms of the device yield as a function of sample number. Samples 1 and 2 utilize the hexagonal line alone and the back-filling process alone, respectively. Sample 3 employs the combined effect of the two methods, which is our approach. The inset represents the switching success (yellow) and failure (green, blue), respectively. Memristors without distinguishable ON and OFF states were considered as switching failures. n A distribution map of a 32 × 32 crossbar circuit exhibiting switching success and failure as yellow and black boxes, respectively. o, p A magnified view of the SEM image at a certain crosspoint for samples 1 and 3. This indicates that the back-filling process can mitigate the rabbit ear formed along the bottom electrode lines to some degree. The scale bar for (o, p) is 1 μm. q, r Top-view SEM images of 4 × 5 sub-arrays for samples 2 and 3, revealing a clear difference in line shape. This can prevent the reduction of the applied electric field across multiple memristors. The scale bar for (q, r) is 10 μm.
