Fig. 1: Device structure and fundamental principle.

a Three factors for increasing the storage state number for FGMs (Floating-gate memories): expanding the dynamic range, which means increasing the ratio of on-state current (I_on) to off-state current (I_off); enhancing the stability of conductance states; lowering device noise, which refers to conductance state fluctuations (σ_n or σ_n^’). b An optical microscopy image and schematic diagram of the MoS₂ FGM, where Bi/Au is used as the contact electrodes, Cr/Au as the control gate, Pt as the floating gate, and Al₂O₃ as the dielectric layer. The programming and erasing operations occur at the control gate region. c, d Output and transfer curves of FGMs with Bi/Au (green lines) and Cr/Au (blue lines) contacts. J_DS is the source-drain current density, while V_DS and V_GS are the source-drain voltage and gate voltage, respectively. e, f The programming and erasing processes using dual-pulse (yellow lines) and single-pulse (green lines) programming methods. Insets show the dual pulse programming scheme. A tune voltage pulse (V_tune) with an opposite sign follows the programming/erasing voltage pulse (V_program/V_erase) to achieve stable states. g, h The I_DS-time curves and noise current spectrum (S_I)-I_DS curves of FGMs with Bi/Au (brown lines) and Cr/Au (yellow lines) contacts.