Fig. 3: Construction methods for complex logic functions.
Flowchart for constructing a full adder based on the LF-QM method, including a logical schematic, b truth table, c simplified Boolean functions of digital outputs (LF-QM expressions), and circuit network layout, and d experimental Boolean response under four input states. e Comparative analysis of the number of units required for different levels of functional complexity in state-of-the-art mechanical computing technologies3,7,8,9,20,28,50,51. Experimental demonstration of an asynchronous two-bit binary counter, including f logical schematic (Top), a mobile robot with an integrated counter and a seven-segment display for visualization (Bottom), g circuit network layout, with regions enclosed by the same colored block belonging to the same unit, h two-layer experimental platform comprising a lower Magnetic Field Region and an upper Robotic Path, and i real-time digital outputs of A0 and A1 units characterized by voltages collected via a wireless acquisition module. In (h), the orange ellipse represents the magnetic field, while the arrow at its center indicates the direction of the magnetic field.
