Fig. 5: Programmability of the MPGA.

a Workflow diagram of the MPGA. b Layout of individual LMs in a 2 × 2 array for general-purpose computation. The LMs at addresses a1–a4 are \({m}_{0}^{2}\)(X₁’X₀’), \({m}_{1}^{2}\)(X₁’X₀), \({m}_{2}^{2}\)(X₁X₀’) and \({m}_{3}^{2}\)(X₁X₀), respectively. c Layout of individual LMs in a 2 × 2 array for application-specific computation, specifically for half-adder and half-subtractor functions. The LMs at addresses a1–a4 are XOR, Buffer, Not, and Buffer, respectively. d Logical schematics of the half-adder and half-subtractor. The half-adder is implemented by traversing addresses 1, 3, and 4, while the half-subtractor is implemented by traversing addresses 1, 2, and 4. e Experimental images of computations 0−1 = −1 and 0 + 1 = 1. Green and purple trajectory lines with indicator arrows represent the movement paths of the addressing robot for performing the half-adder and half-subtractor computations, respectively. Indicator LEDs for computational outputs and active positions are magnified for clarity.