Fig. 6: Programmable implementation of a 2-bit adder and a 2-bit multiplier. | Nature Communications

Fig. 6: Programmable implementation of a 2-bit adder and a 2-bit multiplier.

From: General-purpose mechanical computing enabled by origami circuit reconfiguration with robotic addressing and activation

Fig. 6

a Schematic illustration of the programmable functionality of a 2-bit adder and a 2-bit multiplier based on a 4-input, 4-output MPGA. b Top view and circuit layout details of a 4-input, 1-output MPGA, with the four rows of modules (from top to bottom) corresponding to inputs A1, A0, B1, and B0. c Structural details of a 4-input, 1-output MPGA, comprising 15 m0 modules and 15 m1 modules, corresponding to Not(1) and Buffer(1) units, respectively. The inputs for the first three rows (A1, A0, B1) are fixed at logic 0, while the bottom row (B0) is maintained in an undefined state, with all outputs fixed at logic 0. d Experimental demonstration of the programmed address paths in MPGA2 for generating P1(2-bit multiplier) and S1(2-bit adder) outputs. Purple and green trajectory lines with indicator arrow represent the movement paths of the addressing robot for performing the P1 and S1 computations, respectively.

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