Fig. 1: Integration process and structural characterisation of van der Waals (vdW) interface-integrated high-κ/transition-metal dichalcogendie (TMD; n-, p-) gate stacks. | Nature Communications

Fig. 1: Integration process and structural characterisation of van der Waals (vdW) interface-integrated high-κ/transition-metal dichalcogendie (TMD; n-, p-) gate stacks.

From: High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems

Fig. 1: Integration process and structural characterisation of van der Waals (vdW) interface-integrated high-κ/transition-metal dichalcogendie (TMD; n-, p-) gate stacks.

a Schematic illustration of the universally applicable HfO2 integration on TMDs, achieving an atomically flat vdW interface via transfer and plasma oxidation. b, c Cross-sectional scanning transmission electron microscopy (STEM) images of fabricated HfO2/MoS2 and HfO2/WSe2 gate stack, retaining the pristine vdW gap as a clean vdW interface after plasma oxidation (upper panels: before HfSe2 oxidation; lower panels: after full conversion of HfSe2 to HfO2). The arrows and boxes in pale pink and pale blue represent the HfO2/MoS2 and HfO2/WSe2 gate stacks, respectively. d, e Higher-resolution STEM images (left panels) showing the atomically flat vdW interface between fully converted HfO2 and TMDs (MoS2, WSe2). The corresponding intensity profiles (right panels) further confirm the presence of a vdW gap (≈0.3 nm) at the HfO2/TMDs (MoS2, WSe2) interface, comparable to the interlayer spacing (≈0.3 nm) of MoS2 and WSe2.

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