Introduction

The International Roadmap for Devices and Systems (IRDS) outlines a vertically integrated complementary metal-oxide-semiconductor (CMOS) architecture as a transformative strategy for advancing ultimate scaling design rules1. Within this framework, two-dimensional (2D) van der Waals (vdW) semiconductors, particularly transition metal dichalcogenides (TMDs) such as MoS2 and WSe2, are representative of n- and p-type channels. Known for their immunity to short-channel effects, chemical stability, and high mobility, they outperform strained silicon with similar thinness2,3,4, making them the most compelling combination for realising future three-dimensional (3D) logic gates5,6. Furthermore, their ability to reduce the overall stack height effectively suppresses parasitic capacitance, whereas their high on-current densities enable exceptional operating frequencies, making them a highly attractive option for advanced 3D integrated circuits7. Despite this promising potential, significant challenges remain for their use in practical applications. The most critical concern is exploring universal high-κ dielectric integration with superior interfacial and dielectric properties for both n- and p-type field-effect transistors (nFET and pFET), respectively, thereby improving gating efficiency in terms of scaled equivalent oxide thickness (EOT) and achieving desirable 3D complementary logic functionality for high-speed and low power dissipation systems considering industrial requirements8.

To date, recent advancements in high-κ dielectric integration on 2D semiconductors have primarily involved direct deposition, native oxidation, and vdW integration. Atomic layer deposition (ALD) is the most preferred method for high-κ dielectric integration owing to its industrial compatibility and capability for wafer-scale integration. However, the dangling-bond-free surface of 2D semiconductors reduces the surface reactivity during initial nucleation, fundamentally leading to non-uniform dielectric formation9,10,11. To address this issue, surface functionalisation using O2 plasma, UV-O3, and electron-beam irradiation has been introduced to assist the adsorption of precursors by creating activated sites12,13,14,15,16,17,18. However, directly modified interfaces introduce defect sites, including chalcogen vacancies in the channel, oxygen vacancies in the dielectric, and impurities, resulting in threshold voltage instability, increased subthreshold swing (SS), and hysteresis19,20,21,22. Sb2O3, an inorganic molecular crystal, is an alternative interlayer material23. Its cage-like molecular structure, which is free of dangling bonds, has shown improvements in the interfacial quality, allowing for high-quality ALD-grown dielectrics on 2D semiconductors. However, its relatively low dielectric constant ( ≈ 11.5) and unproven versatility in other TMDs require further consideration.

Native oxidation, an in-situ process, facilitates chemical conversion within the channel layer, resulting in an atomically sharp interface that is comparable to the SiO2/Si interface24. We recently demonstrated the layer-by-layer oxidation of 2D HfSe2 and HfS2 into HfO2 and particularly for the HfSe2 case achieved a low interface charge trap density (Dit) of ≈5 × 1010 cm−2 eV−1 25. Moreover, single-crystalline Bi2SeO5 native oxide layers have been successfully integrated even in vertically grown 2D Bi2O2Se channels, enabling fin field-effect transistors and broadening structural freedom26,27,28. However, this methodology is only feasible for a limited number of channel materials, excluding Mo- and W-based TMDs, which have the highest application potential, thereby restricting its wide adoption in future 3D complementary logic systems.

vdW integration, which forms an atomically smooth vdW interface between the dielectric and channel (i.e., physical separation with weak vdW coupling), ensures the chemical inertness and mechanical stability of 2D semiconductors, making it a promising approach for dielectric integration29,30,31. vdW integration is typically achieved via transfer methods and can be categorised by the transferred materials, such as single-crystalline dielectrics, amorphous dielectrics, and transferred and oxidised dielectrics. Since the discovery of 2D layered crystalline dielectrics, h-BN has been widely adopted because of its dangling-bond-free surface, which allows for the formation of a clean vdW interface32. Its large-scale synthesis using up to 4-inch wafers has also been demonstrated33, but its inherently low dielectric constant remains a significant limitation for low-power applications. Bi2SeO5 is a single-crystalline vdW-layered dielectric with a high dielectric constant (≈16.5). This system has shown potential, but its practical device applications and interface quality require further comprehensive verification34. Zeng et al. reported single-crystalline Al2O3 using intercalative oxidation on an aluminium surface and demonstrated a remarkably reduced interfacial trap density (≈8.4 × 109 cm-2 eV-1) with MoS235. They fabricated MoS2 FETs that exhibited a low SS of 61 mV/dec at room temperature. Despite this strategy, the minimum EOT is limited to ≈0.77 nm owing to the lowered dielectric constant after crystallisation, which remains a challenge for future scaled nodes. Recently, the transfer of ALD-grown amorphous dielectrics (e.g., HfO2 and Al2O3) on a wafer scale has been proposed as an alternative36,37. However, the use of sacrificial layers (e.g., PVA and TRT/PMMA) during the peel-off and lamination processes causes interfacial contamination, leading to increased SS and performance variability38,39,40,41. The most recent emerging strategy for vdW integration is to transfer and oxidise the dielectric, which process utilises Hf- and Zr-based TMDs as precursors. Jing et al. reported ultrathin amorphous HfOx sandwiched within vdW heterostructures obtained by the selective thermal oxidation of HfSe2 precursors, demonstrating a low leakage current density (≈10−6 A/cm2) and high breakdown field (≈9.5 MV/cm)42. Furthermore, the integration of high-κ HfOx on MoS2 has been achieved by oxidising transferred 2D HfS2 layer with UV-ozone treatment, showing promise as a 2D-compatible dielectric with a vdW interface and a low SS of 63.1 mV/dec43. Despite the progress in vdW integration, recent efforts have predominantly focused on n-type 2D semiconductors, leaving p-type 2D semiconductors underexplored. Moreover, the integration of these 2D semiconductors into circuit-level applications within 3D CMOS architectures remains unaddressed, revealing a critical gap toward realising 3D logic gates. Therefore, the scalable and advanced vdW integration of high-κ dielectric must be studied to successfully realise future 2D semiconductor-based 3D CMOS systems.

In this paper, we present a scalable approach for integrating vdW-interface-based high-κ dielectrics on both n- and p-type 2D semiconductors. By transferring HfSe2, a high-κ precursor, onto both MoS2 and WSe2 channels and subsequently converting HfSe2 into HfO2 via controllable plasma oxidation, an atomically flat vdW interface with a suppressed interface trap density (Dit, HfO2/MoS2: ≈7.1 × 1010 cm−2 eV−1 and HfO2/WSe2: ≈8.4 × 1010 cm−2 eV−1) was achieved. Large-scale ab initio molecular dynamics (AIMD) simulations based on density functional theory (DFT) were performed to clarify the mechanism of the layer-by-layer oxidation in HfSe2 and explain why the HfSe2-to-HfO2 conversion facilitates clean vdW interfaces with MoS2 or WSe2. The HfO2 layer exhibited a high dielectric constant (≈23) and low gate leakage current across various EOT ranges. The universality of this approach was further demonstrated by fabricating MoS2 nFET and WSe2 pFET systems, which exhibited nearly ideal SS values of 61 and 63 mV/dec (over four orders of magnitude of IDS) at room temperature (300 K), along with a high on-off ratio (≈108) and negligible hysteresis (≈3 mV). The consistent results observed in 40 devices further suggest the reproducibility of the proposed vdW interface-integrated FETs. Furthermore, we fabricated a vertically interconnected complementary field-effect transistor (CFET) inverter by sequentially stacking the MoS2 nFET and WSe2 pFET systems, demonstrating a high inverter gain (≈115), noise margin (NML, NMH = 98% of 1/2VDD), and reduced static power consumption (≈19 pW). Subsequently, ring oscillators (ROs) incorporating the proposed CFETs were demonstrated. These ROs achieved a reduced propagation stage delay time (≈1.83 ns), demonstrating their potential for high-performance circuit applications. These findings represent a major step forward in achieving scalable and universal vdW interface engineering, laying the groundwork for the future development of integrated circuits with 3D logic gates for post-Si technology.

Results

Universal high-κ dielectric integration with a vdW interface

Figure 1a illustrates the integration process for a vdW-interface high-κ dielectric onto 2D semiconductor channels. The HfSe2 layer was transferred onto the channel materials and fully oxidised at an oxidation rate of ≈2.1 nm/min under pre-investigated oxygen plasma conditions (see details in the Methods section and Supplementary Figs. 2–4). In this manner, only HfSe2 was fully converted into the HfO2 dielectric while sustaining the atomically flat vdW interface, thereby preserving the underlying channel properties (Supplementary Figs. 5–9). The detailed mechanism of the vdW interface-terminated oxidation process is discussed in the following section. This universal approach was implemented to fabricate both HfO2/MoS2 and HfO2/WSe2 gate stacks, which exhibited atomically smooth vdW interfaces (Fig. 1b, c). Notably, the pristine vdW gap of the HfSe2/TMD (MoS2, WSe2) heterostructure remained intact after oxidation, maintaining the integrity of the clean vdW interface in the HfO2/TMD (MoS2, WSe2) heterostructures. The high-resolution STEM images in Fig. 1d, e further indicate that HfO2 formation is limited to the vdW gaps above the channels, sustaining the channel crystallinity. The observed interfacial gap (≈0.3 nm) between HfO2/TMD (MoS2, WSe2) is comparable to the physical vdW gap (defined as the chalcogen-to-chalcogen distance) between MoS2 and WSe2 (Fig. 1d, e). Furthermore, uniform coverage with consistently high vdW interface quality was observed in individual samples, and reproducible morphological results were obtained across multiple samples (Supplementary Fig. 10 and 11), demonstrating the robustness of the proposed vdW interface approach and its potential for broad applicability in various 2D semiconductor device platforms. The robust vdW interface maintained throughout thermal cycling further demonstrates its thermal stability (Supplementary Fig. 22). The scalability of this methodology toward wafer-scale integration will be further investigated in our future work through the combination with large-area 2D precursor formation approaches.

Fig. 1: Integration process and structural characterisation of van der Waals (vdW) interface-integrated high-κ/transition-metal dichalcogendie (TMD; n-, p-) gate stacks.
Fig. 1: Integration process and structural characterisation of van der Waals (vdW) interface-integrated high-κ/transition-metal dichalcogendie (TMD; n-, p-) gate stacks.
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a Schematic illustration of the universally applicable HfO2 integration on TMDs, achieving an atomically flat vdW interface via transfer and plasma oxidation. b, c Cross-sectional scanning transmission electron microscopy (STEM) images of fabricated HfO2/MoS2 and HfO2/WSe2 gate stack, retaining the pristine vdW gap as a clean vdW interface after plasma oxidation (upper panels: before HfSe2 oxidation; lower panels: after full conversion of HfSe2 to HfO2). The arrows and boxes in pale pink and pale blue represent the HfO2/MoS2 and HfO2/WSe2 gate stacks, respectively. d, e Higher-resolution STEM images (left panels) showing the atomically flat vdW interface between fully converted HfO2 and TMDs (MoS2, WSe2). The corresponding intensity profiles (right panels) further confirm the presence of a vdW gap (≈0.3 nm) at the HfO2/TMDs (MoS2, WSe2) interface, comparable to the interlayer spacing (≈0.3 nm) of MoS2 and WSe2.

Mechanism of the formation of vdW HfO2/TMD interfaces

To clarify the mechanisms underlying the universal formation of atomically clean HfO2/TMD vdW interfaces via the oxygen plasma oxidation of HfSe2, we performed AIMD simulations within the DFT framework. While extensive AIMD simulations have been performed for the Si oxidation44,45, to our knowledge, the corresponding AIMD simulation study for HfSe2 or is non-existent25,46. Based on extensive testing, we initially established an AIMD protocol that simulates the oxygen plasma HfSe2 oxidation process (Fig. 2a). Briefly, it consists of (1) the introduction of several randomly distributed singlet O (1D) atoms dropping onto the HfSe2 surface with normal-direction velocities assigned according to the Maxwell-Boltzmann distribution, (2) a multiple picosecond (ps) NVE-ensemble oxidation MD run that captures the incorporation of O atoms into HfSe2 and the resulting migration and cluster formation of extracted Se atoms, (3) the removal of free-floating Se atoms or clusters, (4) a 1 ps NVT-ensemble quenching MD run with a Nosé-Hoover thermostat, and (5) the repetitive applications of steps (1)–(4) for the progressively oxidising HfSe2 (HfSexOy) model (Supplementary Figs. 12–14). Throughout MD simulations, reflecting the low-temperature plasma experimental condition, we adopted a temperature of 500 K.

Fig. 2: Ab initio molecular dynamics (AIMD) simulations of HfSe2 and HfSe2/TMD (HfSe2, MoS2, and WSe2) interface oxidations.
Fig. 2: Ab initio molecular dynamics (AIMD) simulations of HfSe2 and HfSe2/TMD (HfSe2, MoS2, and WSe2) interface oxidations.
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a A sequence of microcanonical (NVE) and canonical ensemble (NVT) dynamics (highlighted by the light green box) is performed to simulate the oxidation of a monolayer HfSe2. Oxygen atoms are inserted at the start of NVE dynamics (red box), followed by NVT dynamics (blue box) after the removal of floating Se atoms. The striped arrow represents repeated application of the NVE–NVT cycle. b A partially oxidised HfSe2 (O36 model)/pristine HfSe2 structure undergoes further oxidation under the same NVE–NVT scheme, resulting in layer-by-layer oxidation and retention of a vdW gap. c A comparative analysis of O36 model/TMD interfaces within a single NVE dynamics step, where oxygen atoms are directed toward the bottom TMD layer. In HfSe2 (top), oxidation proceeds at the bottom layer, while in MoS2 (middle) and WSe2 (bottom), oxygen atoms primarily passivate the bottom surface of the upper oxide layer.

Applying the alternating NVE-NVT AIMD scheme to a HfSe2 monolayer modelled by a (3×4) supercell (Supplementary Fig. 12) and introducing four impinging O atoms, we first analysed the key atomistic features in the HfSe2 oxidation process (Fig. 2a and Supplementary Fig. 14). Next, as shown in Fig. 2b, we continued the AIMD simulations with an interface model prepared by placing a partially oxidised Hf24Se28O36 (O36) on top of a HfSe2 monolayer (Supplementary Fig. 12) and studied the mechanisms of the layer-by-layer HfSe2 oxidation process. Based on DFT-based energetic analyses, we previously showed that the facile HfSe2-to-HfO2 conversion is allowed because O atoms can replace Se atoms on a HfSe2 surface without a substitution energy barrier25. Through AIMD simulations, we could additionally observe that, upon reacting with HfSe2, impinging O atoms release significant heat (≈7 eV per O atom) and, due to thermal vibrations and strong Hf-O interactions, they rapidly (within a few ps) diffuse to Se sites (Supplementary Fig. 13). As the oxidation proceeds and the number of neighbouring O atoms increases in the top HfSexOy layer, Hf atoms that were initially placed planarly began to reconfigure vertically. This results in the formation of voids within the HfSexOy layer, which should act as pathways for the insertion (extraction) of O (Se) atoms into (out of) the deep HfO2/TMD interfacial regions. At the same time, the displaced Se atoms free floated on the HfSexOy surface and upon meeting other Se atoms formed Se clusters. We then observed that these mobile Se atoms remaining at the HfSexOy/HfSe2 interface play an important role in the layer-by-layer oxidation process by preserving the vdW gap until the full HfSexOy-to-HfO2 conversion is completed25.

To examine whether WSe2 and MoS2 behave differently from HfSe2 in forming clean HfO2/TMD vdW interfaces, we next considered a slightly non-ideal O excess condition that will lead to the breakdown of the layer-by-layer oxidation process for HfSe2. Specifically, as shown in Fig. 2c, we prepared the corresponding O36 HfSexOy/MoS2 and HfSexOy/WSe2 interface models (see also Supplementary Fig. 12) and (rather than dropping from the top) introduced four energetic O atoms into the HfSexOy/TMD interfacial region and repeated AIMD simulations. For the HfSexOy/HfSe2 case, we first confirmed that the second bottom HfSe2 layer begins to oxidise in the NVE run as in the first top HfSe2 layer (Fig. 2c top panel). On the other hand, for the HfSexOy/MoS2 and HfSexOy/WSe2 cases, we found that the O atoms cannot oxidise the top surface of MoS2 or WSe2 and continue oxidising the bottom side of HfSexOy (Fig. 2c middle and bottom panel). This difference indicates that compared with HfSe2, which requires precise control of the layer-by-layer process, achieving clean HfO2/TMD vdW interfaces based on plasma oxidation should be easier with MoS2 or WSe2 (Supplementary Figs. 15 and 16). This is in fact consistent with our experimental observations, indirectly validating our AIMD simulations.

Electrical performance of vdW interface-integrated FETs

Figure 3a shows a schematic of the FETs fabricated with the vdW interface-integrated HfO2/MoS2 and HfO2/WSe2 gate stacks, thereby integrating the MoS2 nFET and WSe2 pFET (see the Methods and Supplementary Fig. 1). Optical images and the output characteristics of these devices are shown in Supplementary Fig. 19. The quality of the vdW interfaces between the HfO2 and TMD channels was investigated using multi-frequency C−V measurements (Fig. 3b). The extracted interface trap densities (Dit) for HfO2/MoS2 and HfO2/WSe2 were suppressed to ≈7.1 × 1010 and ≈8.4 × 1010 cm−2 eV−1, respectively, aligning with the structural and theoretical clarifications discussed above (see details of the measurements and analysis in Supplementary Fig. 17). A high dielectric constant (κ = ≈23; see Supplementary Fig. 17) and low gate leakage current were consistently achieved in EOT ranges of 0.5–2.5 nm (Supplementary Fig. 18), indicating high-quality dielectric characteristics. The suppressed leakage current, compared with the crystalline phase, further underscores the intrinsic advantage of maintaining the amorphous phase to ensure low-power device integrity (Supplementary Fig. 19). Notably, the fabricated MoS2 nFET and WSe2 pFET exhibited near-ideal SS values of 61 and 63 mV/dec (over four orders of IDS) at room temperature (300 K), along with a high on-off ratio of ≈108 and low gate leakage current of ≈10-6 A/cm2. (Fig. 3c). This superior device performance was primarily attributed to the seamless formation of HfO2 on the TMD channels with a well-preserved vdW interface, which suppressed defect formation. The reproducibility of the vdW interface-integrated FETs was demonstrated by the consistent results observed in 40 MoS2 and WSe2 FETs, all fabricated using the same process (Fig. 3c and Supplementary Fig. 23). The stability and reliability of the fabricated FETs were further corroborated by time-dependent electrical performance and bias–temperature stress durability (Supplementary Figs. 24 and 25).

Fig. 3: vdW interface-integrated MoS2 n-type field-effect transistor (nFET) and WSe2 p-type field-effect transistor (pFET).
Fig. 3: vdW interface-integrated MoS2 n-type field-effect transistor (nFET) and WSe2 p-type field-effect transistor (pFET).
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a Schematic of the top-gated FETs fabricated with the vdW interface-integrated HfO2/TMD (MoS2, WSe2) gate stack (≈5 nm MoS2 and WSe2, ≈10 nm HfO2; Channel length and width are 3 µm, respectively). b Extracted interface charge trap density (Dit) as a function of frequency using the conduction method from multi-frequency capacitance–voltage measurements. c Cumulative transfer characteristics of 40 MoS2 nFETs and WSe2 pFETs with the median transfer curves highlighted (at VDS = \(\pm\)0.5, respectively). Note that all the devices were measured at gate voltage sweeping speed of 0.025 V/s. Both MoS2 nFET and WSe2 pFET exhibit the near-ideal subthreshold swings (61 mV/dec and 63 mV/dec, respectively, at 300 K) with low gate leakage current of ≈10-13 A. IDS and IGS denote the drain and gate currents, respectively, while VDS and VGS represent the drain-to-source and gate-to-source voltages. SS refers to the subthreshold swing. d–f The full view (d) and enlarged view (e, f) of the dual sweep transfer curves measured at various gate-voltage sweeping speeds, indicating negligible hysteresis of ≈3 mV (Inset: enlarged view of measured hysteresis under gate sweep rate of 0.01 V/s). g–i The full view (g) and enlarged view (h, i) of the dual sweep transfer curves under different gate-voltage sweeping ranges, also exhibiting small hysteresis of ≈3 mV (Inset: enlarged view of measured hysteresis under gate sweep range; −0.5 V to 0.8 V, and 0.5 V to −0.8 V, respectively).

Gate hysteresis is another critical device parameter closely related to the interface quality and defects within the dielectric layer47,48. The hysteresis of the MoS2 nFET and WSe2 pFET was evaluated under varying gate sweeping rates from 0.01 to 0.1 V/s (Fig. 3d). The negligible hysteresis (≈3 mV) indicates that the trap states at the vdW interface and within the HfO2 dielectric were suppressed (Fig. 3e, f). This performance demonstrates an improvement over recently reported vdW interface-integrated high-κ dielectrics on a 2D semiconductor, including GdOCl/MoS2 (≈5 mV), HfO2/MoS2 (≈10 mV), Al2O3/MoS2 (≈10 mV), and Ga2O3/MoS2 (≈60 mV)37,43,49,50. Furthermore, both the MoS2 nFET and WSe2 pFET demonstrated SS values approaching the Boltzmann limit across all sweep rates without degradation over four orders of IDS. Similar results were observed for various gate-sweeping ranges (Fig. 3g–i). Device simulations incorporating various process nodes were also conducted to investigate the SS and on–off ratio variations of the proposed FETs with respect to the different Dit values (Supplementary Table 3 and Supplementary Figs. 26a and 27). These findings confirm that the proposed vdW integration offers a universal and scalable approach for delivering consistent and predictable performances in 2D semiconductor-based electronics, underscoring its potential for the construction of future low-power complementary logic gates.

3D integrated CFET inverter

Recent advancements, including innovative approaches that leverage monolithic 3D integration, have highlighted the feasibility of 2D semiconductor-based vertical CMOS technology51,52,53,54,55,56,57,58. However, the interfacial degradation associated with integrating conventional high-κ dielectrics and 2D semiconductors remains a critical challenge, limiting the performance of future 3D CMOS integrated circuits. In this study, we demonstrate the feasibility of CFETs by sequentially stacking vdW interface-integrated FETs. A schematic of the 3D structure of the proposed CFET, where the top MoS2 nFET and bottom WSe2 pFET are vertically interconnected, is shown in Fig. 4a (see Supplementary Figs. 1, 28 and 29 for details). In this configuration, the MoS2 nFET and WSe2 pFET share a common gate, and the sources are connected to the same metal pad to form a 3D integrated CMOS inverter. The common gate functions as the input voltage (VIN), whereas the connected drains of the nFET and pFET serve as the output voltage (VOUT). Importantly, in the proposed vdW integration system with a high-κ dielectric, the voltage transfer characteristics of the CFET show highly sharp voltage transitions at different supply voltages (VDD) ranging from 0.5 to 2.0 V (Fig. 4b). VOUT is high (logic ‘1’) when VIN is low (logic ‘0’), and VOUT is reduced to a low level (logic ‘0’) when VIN increases (logic ‘1’), demonstrating an ideal logic functionality. The high VOUT near VDD and low VOUT of ≈0.1 mV indicate a well-matched voltage between the two FETs and their low leakage currents, as discussed in the previous section. The voltage gain is boosted with the increase of VDD and reaches a peak value of ≈115 at VDD = 2.0 V (Fig. 4c). In particular, acceptable voltage gains at a scaled VDD of 0.5 V satisfied the minimum requirement for ultralow-power logic applications1,59,60,61,62. Furthermore, the proposed CFET exhibited superior gain and a low-voltage operation capability compared to previously reported CFETs (Fig. 4d). The inverter gain of the fabricated CFET at various supply voltages is among the highest values reported for comparable architectures to date, including conventional Si channels63,64, 2D-Si hybrid channels65,66, and all 2D configurations53,54,67,68,69,70 (also in Supplementary Table 1). The demonstrated voltage gain is essential for signal transmission and logic operations in 3D integrated circuits. Similar results were consistently obtained for 10 CFETs integrated using the same fabrication process (Supplementary Fig. 30). The noise margin is another crucial parameter related to stable inverter operation and desirable circuit performance, and it defines the tolerance of the output signal to the signal interference at the input. The enhanced noise margin derived from the sharp and narrow transition in the voltage transfer characteristics was demonstrated (Fig. 4e). The input voltage is defined as logic high (‘1’) when VIN < VIH and logic low (‘0’) when VIN > VIL, indicating the clear and distinct output logic level in the proposed CFET operation. VOH and VOL represent the ideal logic high and logic low levels of the CFET, respectively. Consequently, the high noise margin (NMH) and low noise margin (NML) were calculated by NMH = VOH - VIH and NML = VIL - VOL, resulting in NMH = 0.975 V (97.5% of 1/2VDD) and NML = 0.985 V (98.5% of 1/2VDD), respectively. Both values approached the ideal noise margin (1/2VDD), indicating the high noise tolerance of the vdW interface-integrated CFET. Moreover, all noise margins exceeded 90% at various supply voltages, further indicating the robustness of the proposed CFETs for multistage operation (Supplementary Fig. 31). The static power consumption of the CFET as a function of VDD is shown in Fig. 4f. Notably, a low peak static power of ≈19 pW at VDD = 0.5 V was demonstrated, which is the most important characteristic of low-power CMOS logic circuits. The proposed CFET demonstrated significantly reduced static power dissipation compared to currently reported CMOS technologies, including both vertical and planar architectures utilising various channel materials (2D channels, 2D/Si hybrid channels, organic channels, and GaN) with enhanced energy efficiency (Fig. 4g and Supplementary Table 1)65,66,67,68,69,70,71,72,73,74. Device simulations based on the proposed structure demonstrated compatibility with current process nodes1, highlighting its potential for energy-efficient, low-power applications in 3D integrated circuits (Supplementary Table 4 and Supplementary Figs. 26b and 32).

Fig. 4: Vertically stacked complementary field-effect transistor (CFET) fabricated with vdW interface-integrated MoS2 nFET and WSe2 pFET.
Fig. 4: Vertically stacked complementary field-effect transistor (CFET) fabricated with vdW interface-integrated MoS2 nFET and WSe2 pFET.
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a Structural schematic of the CFET. GND, VIN, VDD and VOUT represent ground, input voltage, supply voltage and output voltage for the CFET, respectively. b, c Voltage transfer characteristics and the corresponding voltage gain as a function of VDD. d The voltage gain comparison of the CFETs fabricated with 2D semiconductor/Si hybrid channel, 2D semiconductor channel, and Si channel, including proposed vdW interface-integrated CFET53,54,63,64,65,66,67,68,69,70. e Voltage transfer characteristic and its mirror reflection at VDD = 2.0 V. VOH, VOL, VIL, and VIH represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage, respectively. The noise margin is determined by nesting the largest square (grey shaded area). The dashed lines (black) are auxiliary lines for extracting the value of VOH, VOL, VIL, and VIH. f Static power consumption of the proposed CFET as a function of VDD. IDD denotes the supply current. g Comparison of static power consumption at various VDD with literature reports65,66,67,68,69,70,71,72,73,74.

RO integrated with CFETs

Here, we present CFET-integrated ROs, demonstrating a 3D CMOS architecture incorporating 2D semiconductors with the potential for low-power and high-performance computing. A schematic and the corresponding circuit diagram of the five-stage RO are shown in Fig. 5a. The RO was realised by cascading five CFET inverters in a closed-loop configuration. An additional inverter stage served as a readout buffer to isolate the oscillator operation from the measurement setup, ensuring accurate signal extraction without interference. The same configuration applies to the three-stage RO (see Methods and Supplementary Figs. 1 and 33 for details). Figure 5b shows the output oscillation signals of the three- and five-stage ROs measured at VDD = 2.0 V. Both configurations exhibited stable and periodic oscillation with suppressed signal loss. Furthermore, consistent results were also achieved under various supply voltages varying from 0.5 to 2.0 V (Fig. 5c and Supplementary Fig. 34). This is attributed to high-quality vdW interface-integrated FETs and their seamless extension into vertically interconnected high-performance CFET architectures. The corresponding propagation delay time per stage, defined as τpd = 1/2Nf (where N is the number of RO stages and f is the oscillation frequency) at VDD = 2.0 V was ≈1.83 and ≈1.85 ns for the three- and five-stage ROs, respectively. The similar τpd values of these ROs further indicate their stability and robustness. Moreover, the fabricated ROs demonstrated a competitive advantage with low driving voltages and fast propagation stage delay times compared to previously reported ROs fabricated with various 2D semiconductors, organic materials, CNT, oxides, and Si/GaN channels (Fig. 5d and Supplementary Table 2), outperforming the reported experimental results63,67,73,74,75,76,77,78,79,80,81,82. Further optimisation, including the suppression of parasitic capacitances, reduction of contact resistance, and aggressive gate-length scaling is expected to further enhance the signal delivery and overall performance, achieving levels comparable to those of advanced technology nodes (Supplementary Fig. 35).

Fig. 5: Demonstration of ring oscillators fabricated with vdW interface-integrated CFETs.
Fig. 5: Demonstration of ring oscillators fabricated with vdW interface-integrated CFETs.
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a Schematic and the corresponding circuit diagram of the five-stage ring oscillator (RO). b Output signals of three- and five-stage ROs operated at VDD = 2.0 V. c Summarised output frequencies with the corresponding propagation delay times per stage as a function of VDD. The oscillation frequency increases with VDD, exhibiting typical RO behaviour. Maximum/minimum frequencies are 91.5 MHz/52.4 MHz for the three-stage RO, and 53 MHz/32.42 MHz for the five-stage RO, respectively. Both ROs exhibit similar propagation-stage delay times at the same VDD, with the delay time reduced to ≈1.83 ns at VDD = 2.0 V. d Comparison of propagation-stage delay time versus VDD with literature reports (circle three-stage, up-triangle: five-stage, square: seven-stage, pentagon: eleven-stage, diamond: fifteen-stage, hexagon: seventeen-stage)63,67,73,74,75,76,77,78,79,80,81,82.

Discussion

We report universal high-κ dielectric integration with a high-quality vdW interface by converting the transferred HfSe2 on MoS2 and WSe2 into HfO2 via controllable plasma oxidation, preserving the clean vdW interface and channel properties. Atomically flat vdW interfaces of the HfO2/MoS2 and HfO2/WSe2 heterostructures with suppressed Dit values of ≈7.1 × 1010 and ≈8.4 × 1010 cm−2 eV−1 were demonstrated. Consequently, the fabricated MoS2 nFET and WSe2 pFET exhibited near-ideal SS values of 61 and 63 mV/dec, respectively, over four orders of IDS at room temperature (300 K), which is close to the Boltzmann limit, along with a high on–off ratio (≈108) and small hysteresis (≈3 mV).

Based on first-principles molecular dynamics simulations, we provided mechanistic explanations for why the oxygen plasma-induced HfSe2-to-HfO2 conversion serves as a universal strategy for establishing atomically clean vdW HfO2/TMD interfaces and is particularly effective for preparing HfO2/MoS2 and HfO2/WSe2 interfaces.

The vdW interface-integrated CFET, in which the MoS2 nFET and WSe2 pFET were sequentially stacked, demonstrated a high voltage gain (≈115) and low static power dissipation (≈19 pW). Furthermore, the ROs integrated with CFETs demonstrated an enhanced propagation delay time per stage (≈1.83 ns), indicating their potential for high-frequency circuit applications. Our findings provide a pathway toward a broadly applicable framework for integrating high-κ dielectrics with diverse 2D semiconductors through atomically defined vdW interfaces. This approach can be extended to a wide range of material systems and device architectures, offering a versatile platform for future 2D semiconductor-based 3D logic and memory technologies aimed at enhanced scalability and energy-efficient computing.

Methods

Fabrication of the HfO2/TMD heterostructure

The exfoliation and transfer processes were performed in a glove box in a controlled environment to prevent external perturbations (where both the O2 and H2O concentrations were <0.1 ppm). The thickness of the material was first identified using an optical microscope, and then accurately determined using an atomic force microscope. MoS2 and WSe2 were first transferred onto a SiO2/Si substrate, followed by transferring HfSe2. Then, O2 plasma oxidation was performed under fixed conditions (a power of 10 W, flow rate of 5 sccm, and pressure of 470 mTorr) for HfO2 formation as a high-κ gate dielectric with an atomically flat vdW interface. The polymethyl methacrylate (PMMA) layers were spin-coated at 2000 rpm for 5 s and 4000 rpm for 35 s. Each layer was baked at 180 °C for 2 min on a hot plate. Electron-beam lithography (EBL) and electron-beam deposition were used to form source/drain and top-gate electrodes with Au in a high-vacuum chamber (5 × 10−7 Torr).

Fabrication of FET

MoS2 and WSe2 flakes (≈5 nm) were exfoliated using Scotch tape and subsequently dry-transferred onto a SiO2/Si substrate. Source and drain electrodes were defined using standard EBL, followed by the deposition of 10-nm Au metal. After lifting off the metal in acetone, HfSe2 (≈25 nm) was dry-transferred and oxidised for 5 min to form HfO2 layers (≈10 nm) under the given plasma conditions. The top gate was patterned, and a 30-nm Au layer was deposited to serve as the top gate electrode.

Fabrication of CFET and RO

For the CFET, the bottom WSe2 pFET was fabricated using the same procedure as the FET described above. The fabricated HfO2/MoS2 heterostructure was then transferred onto the top gate of the WSe2 pFET via an advanced transfer method using PMMA-coated PDMS considering adhesion and annealed for 30 min to release the HfO2/MoS2 heterostructure via the full decomposition of the PMMA layer. Au source and drain electrodes were then patterned and deposited. In this configuration, the common gate functions as VIN, whereas the connected drains serve as VOUT. These sources act as VDD and GND, respectively. For the ROs, the single-stage fabrication process was identical to that used for the CFETs in both the three- and five-stage designs. To connect each stage, the VOUT of each stage was connected to the VIN of the next stage, and all VDD and GND systems were linked using the same metal pad. Additionally, to reduce the interference between the closed loop and measurement setup, VOUT was connected to an additional readout buffer stage.

Sample characterisation

OM (Olympus, BX51M) and FE-SEM (JEOL, JSM7500F) were used to observe the sizes and colours of the prepared samples and fabricated devices. Raman spectroscopy at an excitation wavelength of 523 nm was used to characterise MoS2, WSe2, and the fully converted HfO2. The thickness of the flakes was determined using an atomic force microscope (Park Systems Corp., NX-10) in the non-contact mode with PPP-NCHR probe tips (nanosensors). The cross-sections were observed using transmission electron microscopy (TEM, JEOL, TEM2100F) at an accelerating voltage of 200 kV.

Electrical characterisation

All the electrical measurements were performed in a probe station (MSTECH) with a vacuum pressure of 10-6 Torr using a semiconductor analyser (Keithley 4200) and an oscilloscope (Tektronix TBS1154). A Keithley 4200 instrument was used to provide the supply voltage to all the devices in this study. A Tektronix TBS1154 instrument was used to measure the output waveforms of the vdW interface-integrated ROs.

Computational details

DFT calculations were performed using the VASP package with the projected augmented wave method83. Many-electron exchange-correlation interactions were treated within the Perdew-Burke-Ernzerhof form of generalised gradient approximation84. The weak long-range dispersion interactions were described within the Grimme’s DFT-D3 method85. The kinetic energy cut-off for the plane wave basis was set at 500 eV, and the 2×4×1 Monkhorst–Pack k-point samplings were used in the structural relaxation for 2D planar structures of TMDs. The atomic structures were optimised until the total energy and the Hellmann-Feynman forces on each atom reached the 10-4 eV and 0.01 eV/Å levels, respectively. AIMD simulations were performed by iterative NVE-NVT dynamics. NVE ensemble dynamics runs a few ps (less than 5 ps) until local configuration of oxygen does not change and NVT ensemble dynamics runs for 1 ps with a Nosé–Hoover thermostat to quench the system to 500 K. Throughout the AIMD procedure, a time step of 1 fs was used, and Brillouin zone sampling was restricted to the Γ-point.

TCAD simulations

Device analysis was performed using Synopsys Sentaurus (Synopsys Inc., Mountain View, CA, USA), a 3D technology computer-aided design (TCAD) software package.