Fig. 4: Vertically stacked complementary field-effect transistor (CFET) fabricated with vdW interface-integrated MoS2 nFET and WSe2 pFET. | Nature Communications

Fig. 4: Vertically stacked complementary field-effect transistor (CFET) fabricated with vdW interface-integrated MoS2 nFET and WSe2 pFET.

From: High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems

Fig. 4: Vertically stacked complementary field-effect transistor (CFET) fabricated with vdW interface-integrated MoS2 nFET and WSe2 pFET.

a Structural schematic of the CFET. GND, VIN, VDD and VOUT represent ground, input voltage, supply voltage and output voltage for the CFET, respectively. b, c Voltage transfer characteristics and the corresponding voltage gain as a function of VDD. d The voltage gain comparison of the CFETs fabricated with 2D semiconductor/Si hybrid channel, 2D semiconductor channel, and Si channel, including proposed vdW interface-integrated CFET53,54,63,64,65,66,67,68,69,70. e Voltage transfer characteristic and its mirror reflection at VDD = 2.0 V. VOH, VOL, VIL, and VIH represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage, respectively. The noise margin is determined by nesting the largest square (grey shaded area). The dashed lines (black) are auxiliary lines for extracting the value of VOH, VOL, VIL, and VIH. f Static power consumption of the proposed CFET as a function of VDD. IDD denotes the supply current. g Comparison of static power consumption at various VDD with literature reports65,66,67,68,69,70,71,72,73,74.

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