Abstract
The rapid expansion of AI models has intensified concerns over energy consumption. Analog in-memory computing with resistive memory offers a promising, energy-efficient alternative, yet its practical deployment is hindered by programming challenges and device non-idealities. Here, we propose a software-hardware co-design that trains randomly weighted resistive-memory neural networks via edge-pruning topology optimization. Software-wise, we tailor the network topology to extract high-performing sub-networks without precise weight tuning, enhancing robustness to device variations and reducing programming overhead. Hardware-wise, we harness the intrinsic stochasticity of resistive-memory electroforming to generate large-scale, low-cost random weights. Implemented on a 40 nm resistive memory chip, our co-design yields accuracy improvements of 17.3% and 19.9% on Fashion-MNIST and Spoken Digit, respectively, and a 9.8% precision-recall AUC improvement on DRIVE, while reducing energy consumption by 78.3%, 67.9%, and 99.7%. We further demonstrate broad applicability across analog memory technologies and scalability to ResNet-50 on ImageNet-100.
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All data supporting the findings of this study are provided in the main text and the Supplementary Information. Processed datasets are available in the GitHub82.
Code availability
The code supporting the findings of this study is available at the GitHub82.
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Acknowledgements
This work was supported in part by the Innovation 2030 for Science and Technology (Grant No. 2021ZD0201203), the National Natural Science Foundation of China (Grant Nos. 62374181, U2341218, 92464201, 62488101, and 62322412), the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDA0330100), the Hong Kong Research Grants Council (Grant Nos. 17212923, C1009-22G, C7003-24Y, and AOE/E-101/23-N), and the Shenzhen Science and Technology Innovation Commission (Grant No. SGDX20220530111405040).
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Z.W. and Y.L. conceived the work. Y.L., So.W., Y.Z., Sh.W., B.W., W.Z., and Y.H. contributed to the design and development of the models, software, and hardware experiments. Y.L., So.W., Y.Z., N.L., B.C., X.C., and Z.W. interpreted, analyzed, and presented the experimental results. Y.L., So.W., and Z.W. wrote the manuscript. Z.W., X.X., and D.S. supervised the project. All authors discussed the results and implications and commented on the manuscript at all stages.
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Li, Y., Wang, S., Zhao, Y. et al. Pruning random resistive memory for optimizing analog AI. Nat Commun (2026). https://doi.org/10.1038/s41467-025-67960-6
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DOI: https://doi.org/10.1038/s41467-025-67960-6
