Introduction

Recent advances in artificial intelligence (AI), particularly deep learning, have revolutionized natural language and image processing, enabling capabilities that increasingly rival human intelligence1,2. However, the trajectory toward larger, more sophisticated models necessitates immense computational resources, raising significant concerns regarding energy consumption and environmental sustainability3,4.

Revisiting analog computing—a technique predating digital architectures-presents a compelling solution5. By harnessing emerging analog devices such as resistive memory6,7,8,9,10, analog computing processes informative analog signals directly, enhancing energy efficiency in three fundamental ways11,12,13,14,15,16,17. First, traditional digital systems physically separate memory and processing units, incurring substantial latency and energy overheads due to frequent data shuttling-the so-called von Neumann bottleneck18,19,20,21,22,23. In contrast, analog resistive memory collocates storage and processing within the same physical device24,25,26,27. Second, as complementary metal-oxide-semiconductor (CMOS) transistors approach physical scaling limits, the pace of Moore’s law is slowing28,29,30,31. Unlike CMOS, analog resistive memory offers high scalability and stackability12,32,33,34,35,36. Third, while standard digital memory (e.g., dynamic random access memory, DRAM) is volatile, non-volatile analog resistive memory retains data without a continuous power supply37,38,39,40,41,42,43,44,45.

Despite these advantages, emerging analog computing systems face persistent hurdles: programming non-idealities and high programming costs. Analog resistive memory exhibits inherent stochasticity and nonlinearity during programming46,47,48,49,50,51,52,53. Furthermore, the energy and time overheads associated with programming these devices are substantially higher than those of their digital counterparts54,55,56. Consequently, harnessing the efficiency of analog computing while mitigating these programming drawbacks remains a major open challenge for the AI hardware and electronics communities.

To address these challenges, we introduce a software-hardware co-design framework based on edge-pruning topology optimization for randomly weighted resistive memory neural networks. Inspired by clipped Hebbian-rule-based structural plasticity57, this approach emulates the brain’s postnatal development: synaptic overproduction, consolidation of functional synapses, and the elimination of redundant ones following extended learning58,59. In contrast to conventional weight optimization methods that rely on precise tuning of resistive memory conductance12,14,15,42,60,61,62, our strategy directly engineers the topology of a randomly initialized network by selectively “turning off" insignificant weights while preserving the rest. Moreover, we leverage the intrinsic electroforming stochasticity of resistive memory to generate large-scale, low-cost hardware random weights, thereby transforming programming variability into a functional asset. Building on the theory by Ramanujan et al.63-which posits that a sub-network pruned from a sufficiently large, randomly weighted network can match the accuracy of a fully optimized one-we physically reset (or set) resistive memory to prune (or reinstate) network edges. By avoiding precise programming, our approach is inherently robust to device non-idealities and eliminates the laborious conductance tuning and verification required in traditional optimization.

We validate our co-design on three representative tasks-image classification, audio classification, and image segmentation-using a hybrid analog-digital system featuring a 40 nm, 256 K resistive memory-based in-memory computing core. With identical network architectures and parameter counts, our approach achieves accuracy improvements of 17.3% and 19.9% on the Fashion-MNIST and Spoken Digit datasets, respectively, while reducing programming operations by 99.94% and 99.93% compared to hardware-in-the-loop weight optimization. The corresponding scaled inference energy per sample is reduced by 78.3% and 67.9% relative to state-of-the-art GPUs. Additionally, simulations of U-Net segmentation on the DRIVE dataset yield an area under the precision-recall curve (PR-AUC) of 0.91 and a receiver operating characteristic (ROC) AUC of 0.97 (improvements of 9.8% and 2.0% over GPUs), accompanied by a 99.7% reduction in inference energy enabled by in-memory computing and sparsity. To further demonstrate scalability, we simulate our co-design with ResNet-50 on ImageNet-100, achieving an average Top-1 accuracy of 87.6% alongside 99.3% energy savings. This work offers a universal solution for AI leveraging analog computing with emerging resistive memory (see Supplementary Figs. 13,14 and Supplementary Tables 11,12 for Llama 364,65 LoRA66 fine-tuning using edge-pruning topology optimization).

Results

Software-hardware co-design: edge-pruning topology optimization for randomly weighted resistive memory neural networks

Figure 1 schematically illustrates the proposed software-hardware co-design, featuring edge-pruning topology optimization applied to a randomly weighted resistive memory neural network.

Fig. 1: Software-hardware co-designed edge-pruning topology optimization.
figure 1

Comparison between the proposed resistive-memory-based software-hardware co-design and conventional GPU-based weight optimization across biological, algorithmic, architectural, and circuit domains. Biologically, the approach is motivated by developmental pruning in the human brain, where repeated experiences eliminate redundant synapses and preserve critical connections, in contrast to conventional schemes grounded in long-term synaptic plasticity. At the algorithm level, edge-pruning topology optimization adjusts the connectivity of a randomly weighted, overparameterized dense network to form a sparse functional sub-network, distinct from methods relying on precise weight tuning. Architecturally, a hybrid analog-digital system with an analog compute core reduces data movement between memory and processor, addressing the von Neumann bottleneck associated with conventional digital architectures. At the circuit level, resistive memory supports parallel analog matrix multiplication and physically realizes edge pruning. Intrinsic programming stochasticity generates dense random weights (illustrated by the differential-conductance heatmap and histogram), while pruning and reinstatement are implemented by resetting or setting selected differential cell pairs to low- or high-conductance states.

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From a software perspective, our bio-inspired edge-pruning topology optimization emulates the human brain’s postnatal development, characterized by synaptic overproduction, the consolidation of functional synapses, and the elimination of redundant ones following extended learning (Fig. 1, upper left). In contrast to conventional weight optimization methods that fine-tune weights to minimize loss, this approach engineers the network architecture to uncover an effective sub-network without altering weight values. This methodology is grounded in a corollary to the Lottery Ticket Hypothesis63, which posits that pruned sub-networks derived from overparameterized neural networks can achieve accuracy competitive with that of the original, fully optimized networks. As depicted in the second panel of Fig. 1, the process initiates with the random initialization of the resistive memory network via electroforming stochasticity. Each edge is assigned a fixed random weight and a corresponding importance score. During the forward pass, edges with low scores in each layer-identified as redundant-are pruned to define the sub-network structure; if a neuron’s connections are heavily pruned, the neuron itself may be subsequently eliminated (see Supplementary Table 8). In the backward pass, scores are updated, and select edges are reinstated (replaced) to refine the sub-network topology and minimize training error (see “Methods” and Supplementary Table 1 for algorithmic details).

In terms of hardware implementation, the proposed optimization is realized on a hybrid analog-digital computing system comprising two main components: an analog core based on a 40 nm, 256 K resistive memory in-memory computing macro, which generates random weights, accelerates computation-intensive matrix multiplications, and executes edge pruning; and a digital core utilizing a Xilinx System-on-Chip (SoC) (see “Methods”). By collocating weight storage and computation, the analog core significantly mitigates data movement between memory and processing units, thereby offering superior energy efficiency and parallelism compared to conventional digital architectures (see Supplementary Fig. 15 for details on the fully integrated resistive memory chip). Prior to training, the resistive memory array is partitioned into positive and negative conductance sub-arrays (G+ and G−), which encode the weight matrix via differential conductance (Fig. 1, right). Initially insulating, the as-deposited cells display a narrow weight distribution centered near zero. Subsequent electroforming induces random analog weights within the G+ and G− arrays, resulting in differential-pair conductances that follow a mixture of two quasi-normal distributions. This process leverages electroforming stochasticity as an intrinsic entropy source, providing large-scale, low-cost true random weights for the overparameterized network (see Supplementary Table 3 for randomness analysis). During training, unnecessary edges are physically pruned by resetting the corresponding resistive memory differential pair, a process that ruptures the conductive filaments and zeros the conductance. Conversely, to reinstate a previously pruned but critical connection, the pair is set back to a conducting state, restoring the filament (see Methods for reset/set operations). Upon completion of training, the high-performing sub-network is frozen, yielding a conductance distribution characterized by a mixture of three quasi-normal distributions. Unlike conventional pruning strategies that primarily seek to sparsify networks to reduce computational complexity, our topology optimization introduces a training scheme specifically tailored for online learning in CIM edge systems, effectively circumventing weight optimization. This approach successfully mitigates key challenges associated with resistive memory, notably programming non-idealities and high programming costs (see Supplementary Fig. 10 for the impact of programming non-idealities).

Physical origin of resistive memory array programming stochasticity

Resistive memory cells were fabricated at the nanoscale and electroformed under identical conditions. The programmed cells were then sliced using a focused ion beam (FIB) before being examined by a high-resolution transmission electron microscope (TEM) to elucidate the microstructural origin of the programming stochasticity.

Figure 2a shows an optical photo of the resistive memory in-memory computing macro. This monolithically integrated 256 K macro adopts a crossbar structure, with resistive memory cells in each row sharing bottom electrodes and those in each column sharing top electrodes. The cells are integrated with CMOS on a 40 nm standard logic platform between the metal 4 and metal 5 layers via a back-end-of-line process, as revealed by high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) (Fig. 2b). Figure 2c highlights clear differences in cross-sectional HAADF-STEM images between pristine and electroformed cells. In the pristine cell (left), the tantalum and tantalum oxide (Ta/TaOx) resistive layer shows uniform structure (e.g., green-boxed area), whereas electroformed cells (middle and right) display brighter contrast regions (e.g., red-boxed areas) between electrodes, indicating structural variations likely due to conducting channels. To analyze composition, energy-dispersive X-ray spectroscopy (EDS) line scans were performed, revealing that brighter regions (red arrow) have a lower oxygen-to-tantalum ratio than darker regions (green arrow), confirming the presence of conducting channels46,47,67. The red line profiles of the two cells also differ markedly, aligning with the electroforming stochasticity observed in Fig. 2h, i. Complementary low-energy electron energy loss spectroscopy (EELS) plane scans and center-point spectra (Fig. 2d, e) of electroformed cells further demonstrate variations in oxygen-vacancy concentrations and valence between dark (Area1) and bright (Area2) regions. Losses in Area1 (25.2 and 25.1 eV) resemble the plasmon peak of insulating TaO2 (25.7 eV), while those in Area2 (24.6 and 24.4 eV) match metallic TaO (24.5 eV), indicating oxygen-vacancy migration during electroforming67,68-consistent with EDS findings. Additionally, EELS low-loss peak maps visualize the conductive channels, showing oxygen-vacancy-rich TaOx clusters spanning nearly all of Area2, with no complete channels in Area1 (Fig. 2f). The varied patterns of these channels and corresponding EELS-peak distributions (Fig. 2g) underscore the inherent stochasticity of electroforming, driven by thin-film inhomogeneity and random oxygen-ion motion, enabling low-cost, scalable random conductance for physically implementing randomly weighted neural networks.

Fig. 2: Physical and electrical characterization of resistive memory (RM) electroforming stochasticity.
figure 2

a Optical micrograph of the 40 nm, 256 K resistive memory in-memory computing macro alongside a schematic of the crossbar array architecture. b Cross-sectional HAADF-STEM image of the resistive memory array, fabricated between Metal 4 and Metal 5 layers via back-end-of-line processing. c Cross-sectional HAADF-STEM images and EDS line profiles of electroformed resistive memory cells. Red and green arrows indicate the regions corresponding to the red-boxed (distinct structural changes) and green-boxed (no distinct changes) areas, respectively. d, e EELS plane scans (energy range: 15–35 eV, step: 0.05 eV) and corresponding center-point low-loss spectra for two electroformed resistive memory cells. Green (Area 1, insulating) and red (Area 2, conducting) regions correspond to the boxes in (c). f EELS low-loss peak maps of Area 1 and Area 2, where the color gradient from yellow to black indicates increasing oxygen-vacancy concentration. The conductive paths in the two cells exhibit marked geometric differences. g Corresponding EELS-peak distributions derived from (f), with green and red curves representing Area 1 and Area 2, respectively. h Histogram and cumulative probability of electroforming voltages for a 20 × 20 resistive memory array, obtained using a linear voltage sweep starting from 3 V with 0.05 V increments applied to each cell. i Joint distribution of conductance and standard deviation for 128 randomly selected resistive memory differential pairs following 100 pruning and reinstatement cycles. Gray and orange points denote pruned and remaining pairs, respectively. Probability densities for conductance and standard deviation are displayed in the top and right histograms. j Data retention characteristics of 128 randomly selected topology-optimized (TO)-trained resistive memory cells over 10,000 read cycles.

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The intrinsic stochasticity of electroforming is harnessed to physically implement randomly weighted neural networks for the proposed edge pruning topology optimization. Figure 2h illustrates the random weight generation process using the resistive memory array. Initially, electroforming voltages are sampled from a small-scale sub-array, defined as the minimum voltage switching cell resistance from ~30 MΩ to below 300 KΩ. Based on the cumulative probability, a uniform 3.4 V pulse (10 ms width) is applied to the G+ (G−) array at 120 °C, yielding a random conductance matrix with approximately half the cells electroformed and the rest insulating (sparsity of 0.5). High-temperature forming enhances cell retention and Ron/Roff uniformity (see Supplementary Fig. 3). Finally, each cell in the G− array is electroformed to a complementary state relative to G+ (see Supplementary Table 5 for impacts of random weight distributions). During training, weights are pruned by resetting corresponding resistive memory differential pairs. As shown in Fig. 2i, analog hardware weights follow a mixture of three quasi-normal distributions, with pruned pairs exhibiting a mean conductance of ~0.07 μS and low variance (see Supplementary Figs. 5–7 and Notes for robustness studies). Figure 2j demonstrates data retention in resistive memory cells, with minimal conductance fluctuation over 10,000 read cycles (0.1 V amplitude, 2 s width), which mitigates overfitting during training as discussed later (see Supplementary Fig. 2 for 150 °C baking retention tests).

Image classification of FashionMNIST using the co-design

The co-design was evaluated on a 4-layer convolutional neural network (CNN)69—a standard vision model-for classifying the FashionMNIST dataset (simulations were also performed with ConvMixer70 on CIFAR-10 and ResNet-5071 on ImageNet100 to further demonstrate applicability; see Supplementary Figs. 11–12 and Supplementary Table 7).

Figure 3a illustrates example feature maps in garment classification using edge pruning topology optimization on the hybrid analog-digital system. The FashionMNIST dataset comprises 70,000 frontal images across 10 garment categories. Test images are down-sampled to 14 × 14, quantized to 4 bits, and input to a randomly weighted 4-layer CNN with two convolutional and two fully connected layers (see “Methods” for CNN details). Initialized with 62 K random weights (124 K resistive memory cells), the model shows differential conductance heatmaps after electroforming and topology optimization in the upper schematic. Figure 3b depicts the corresponding distributions: post-electroforming weights follow a mixture of two quasi-normal distributions with means of −27.1 μS and 27.2 μS; after optimization, half the pairs are pruned (sparsity of 0.5), adding a third distribution with a mean of −0.05 μS (see Supplementary Fig. 6 for CNN hyperparameter studies). Figure 3c visualizes 3D principal component analysis (PCA) of embedded features for the classification head before and after edge pruning topology optimization, with points color-coded by garment category. Topology optimization transforms overlapping embeddings into distinct clusters, yielding discriminative features.

Fig. 3: Experimental image classification on the FashionMNIST dataset using the co-design.
figure 3

a Schematic of the forward pass for garment classification. Test images are digitally pre-processed and then passed to a randomly weighted four-layer CNN physically implemented on analog resistive memory (RM). The upper panel shows measured hardware weights after electroforming and topology optimization, where pruned cells are near zero conductance (white) and retained cells are fixed at conducting states (blue and red). b Corresponding hardware weight distributions after electroforming and edge-pruning topology optimization, forming a mixture of three quasi-normal distributions with enlarged sense margins after pruning. c 3D PCA of feature embeddings after electroforming and after topology optimization, where the latter exhibits well-separated clusters. d Measured classification accuracy over 65 training epochs. Hardware topology optimization (TO) reaches 87.4% accuracy −7.7% higher than hardware weight optimization (WO) with unrestricted updates, and within 0.4% of the software WO baseline. When the WO programming count is capped at 2.6 million via a gradient threshold-comparable to TO's 2.3 million per-cell updates-its accuracy drops by 17.3%. e Experimental confusion matrix, dominated by diagonal entries. f Breakdown of programming counts for hardware-in-the-loop WO and TO. TO reduces weight updates by 99.94% relative to WO. g Inference energy for a single image. Left: the scaled hybrid system achieves a 78.3% energy reduction compared with a GPU, enabled by the software-hardware co-design. Right: TO further cut RM energy by 30.6% relative to WO due to sparsity.

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As shown in Fig. 3d, the experimental edge pruning topology optimization (hardware TO) achieves a classification accuracy of 87.4% compared with 79.7% of hardware weight optimization (hardware WO) with free updates, as the latter is affected by programming noise. This corresponds to a 0.4% accuracy difference compared to the software weight optimization (software WO) baseline on GPU. The edge pruning topology optimization also exhibits higher learning efficiency, showing a 17.3% accuracy margin over weight optimization with gradient threshold under the same budget of weight updates (see Methods for weight optimization details). Additionally, hardware-in-the-loop TO improves accuracy by 0.9% over software TO on GPU, mainly by mitigating overfitting via RM read noise (see Supplementary Fig. 9 for read noise impacts). This accuracy is confirmed by the predominantly diagonal confusion matrix in Fig. 3e. Figure 3f compares training complexity: TO reduces hardware weight updates in convolutional and fully connected layers by 99.74% and 99.98% on average (for fair comparison, protocols are initialized with similar parameter sizes and terminated at comparable accuracy; see Methods and Supplementary Data 1). Figure 3g contrasts single-image inference energy between the hybrid system (~3.67 μJ) and GPU (~5.76 μJ). Scaling the 40 nm design to 5 nm (matching GPU node) reduces hybrid energy to ~1.25 μJ, yielding 78.3% savings. The right panel highlights TO’s sparsity benefit, cutting RM forward-pass energy to ~12.94 nJ versus ~18.65 nJ for WO, demonstrating 30.6% energy saving (see Supplementary Tables 4, 9–10, Supplementary Note 1, and Supplementary Data 4 for energy estimation details).

Audio classification for Spoken Digit with the co-design

In the second experiment, the co-design was applied to audio classification using a convolutional recurrent neural network (CRNN)72—a standard model for extracting spatial and temporal audio features via convolutional and recurrent layers. The Spoken Digit dataset73 was used, which includes 3000 recordings from 6 speakers sampled at 8 kHz.

Figure 4a illustrates experimental forward-pass feature maps on the hybrid analog-digital system. Spoken digits are transformed to the frequency domain and converted into 23 × 15 acoustic feature maps, then fed into a randomly weighted 5-layer CRNN with 2 convolutional layers, 1 recurrent layer, and 2 fully connected layers (see “Methods” for CRNN details). The model incorporates 68.5 K stochastic weights, realized via 137 K randomly initialized resistive memory cells. Hardware weight heatmaps after electroforming and edge pruning are shown in the upper schematic. After electroforming, weights in convolutional, recurrent, and fully connected layers follow a mixture of two quasi-normal distributions with means of −27.3 μS and 27.1 μS (Fig. 4b, left). During topology optimization, half the differential pairs (sparsity of 0.5) are reset to near-zero conductance, with remaining cells fixed, resulting in three quasi-normal distributions (Fig. 4b, right). Figure 4c visualizes 3D PCA of classification-head embeddings after electroforming and topology optimization, with points color-coded by digit category. Similar to image classification, initially overlapping embeddings form distinct clusters post-optimization, indicating discriminative features.

Fig. 4: Experimental audio classification on the Spoken Digit dataset using the co-design.
figure 4

a Schematic of feature maps and selected weights in audio classification. Raw audio is converted to frequency-domain signals, generating 23 × 15 feature maps input to a randomly weighted five-layer CRNN physically implemented on resistive memory (RM). During optimization, pruned cells are reset to off-state (white), while remaining cells retain fixed conductance (blue and red). b Corresponding hardware weight distributions after electroforming and topology optimization. After pruning, nearly half the cells are removed, yielding a mixture of three quasi-normal distributions. c 3D PCA of feature distributions after electroforming and topology optimization, with the latter showing distinct clusters. d Measured accuracy over 60 training epochs. Hardware edge pruning topology optimization (TO) achieves 98.1% accuracy versus 90.8% for hardware weight optimization (WO) with unrestricted updates and 0.2% loss relative to the software WO baseline. Limiting WO programming to 391 thousand (matching TO's 349 thousand via gradient threshold) causes a 19.9% accuracy drop. e Experimental confusion matrix with prominent diagonal elements. f Breakdown of programming counts for hardware-in-the-loop WO and TO. The latter reduces counts by 99.93% compared to unrestricted WO. g Inference energy comparison for a single audio sample. The left panel shows that the scaled hybrid system saves 67.9% energy versus the GPU, enabled by the co-design. The right panel indicates that TO reduces RM energy by 25.9% relative to WO due to sparsity.

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As shown in Fig. 4d, hardware edge pruning topology optimization achieves 98.1% accuracy versus 90.8% for hardware-in-the-loop weight optimization, affected by programming stochasticity-revealing a 0.2% difference relative to the software baseline. Like the image task, hardware topology optimization mitigates overfitting using inherent RM read noise (see Supplementary Fig. 7 for CRNN hyperparameter studies). Performance is confirmed by the confusion matrix in Fig. 4e, featuring prominent diagonals. Figure 4f shows that topology optimization reduces hardware weight updates versus unrestricted weight optimization, with average reductions of 99.64%, 99.97%, and 99.96% in convolutional, recurrent, and fully connected layers, respectively. In Fig. 4g, the energy per spoken-digit inference is ~2.02 μJ on the hybrid system (scaling to ~0.68 μJ at 5 nm) versus ~2.15 μJ on a GPU, corresponding to a 67.9% reduction. The right panel further highlights sparsity benefits, with topology optimization consuming ~4.79 nJ compared to ~6.46 nJ for weight optimization (a 25.9% reduction).

Image segmentation of DRIVE with the co-design

In addition to classification, edge pruning was evaluated on biomedical image segmentation using a U-Net74,75 for the DRIVE76 dataset. DRIVE contains 40 retinal fundus images (565 × 584) for blood vessel segmentation, including 7 images with pathological cases. As illustrated in Fig. 5a, each 584 × 565 image is first partitioned into 96 × 96 patches, which are then processed by a U-Net comprising 2 convolutional layers (input and output), 4 contracting layers (D1-D4), and 4 expansive layers (U1-U4). The network outputs segmented patches of the same size, which are concatenated to form the final segmentation. Figure 5b shows the 768 × 768 simulated weights of the D4 layer after electroforming and pruning. Initial weights are sampled from the measured conductance distribution of electroformed resistive-memory differential pairs. Following topology optimization, 50% of the weights are pruned according to a predefined sparsity of 0.5 (white pixels), while the remaining weights are drawn from the conducting-state distribution. Representative segmentation results are shown in Fig. 5c, where the simulated probability maps, binary predictions, and ground truth (from left to right) exhibit close agreement, delineating major vessels and fine capillaries (see Supplementary Fig. 8 for U-Net hyperparameter studies). Figure 5d, e compares the precision-recall (PR) and ROC curves for software and simulated WO versus simulated edge-pruning TO. The simulated TO achieves PR-AUC and ROC-AUC of 0.91 and 0.97, respectively-only 0.01 below the software WO baseline, yet yielding 9.8% and 2.0% improvements over simulated WO, owing to its robustness to programming stochasticity. The corresponding F1-score (F1) and AUC evolution during training are plotted in Fig. 5f, where simulated TO gradually converges toward the software WO baselines. The confusion matrix in Fig. 5g further validates performance: the simulated U-Net with the co-design attains 97% background and 83% vessel pixel accuracy, closely matching the software WO baseline of 98% and 80% (see Methods for PR, AUC, F1, and accuracy definitions). Figure 5h shows the estimated energy consumption of the GPU computing unit and the RM core for inferring a single image. The energy consumption for the RM core is approximately 3.5 μJ while that of the GPU computing unit is approximately 1339.5 μJ, resulting in a 99.7% energy saving enabled by the co-design.

Fig. 5: Simulated image segmentation on the DRIVE dataset using the co-design.
figure 5

a Illustration of the forward pass for DRIVE dataset segmentation. The 584 × 565 blood vessel image is divided into 96 × 96 patches, segmented by a U-Net with random weights sampled from conducting-state resistive memory differential pair distributions, and concatenated to form the full output. b 768 × 768 random weights of the D4 layer after electroforming and edge pruning. Pruned weights sample from off-state distributions (white), while remaining weights use conducting-state distributions (blue and red). c Segmentation inputs (left), simulated probability and binary blood vessel predictions (middle), and ground truth (right). Predictions closely match ground truth. d PR curve comparison among software weight optimization (WO), simulated WO, and simulated edge pruning topology optimization (TO). TO matches the software WO and outperforms the simulated WO. e ROC curve comparison among software WO, simulated WO, and simulated TO. f Corresponding F1 and AUC curves. g Confusion matrix for simulated pixel-wise blood vessel classification, with dominant diagonal elements. h Estimated inference energy comparison. The RM core achieves 99.7% energy reduction versus software WO on GPU, enabled by the co-design.

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Discussion

In this work, a software-hardware co-designed edge pruning topology optimization for randomly weighted resistive memory neural networks was developed to tackle challenges in implementing AI via analog computing with emerging resistive memory. Hardware-wise, the intrinsic stochasticity of resistive memory electroforming is leveraged to generate large-scale, low-cost random weights and optimize network topology directly through reset operations. This approach avoids precise conductance tuning and provides a time- and energy-efficient, robust method to harness analog in-memory computing benefits for AI. Software-wise, edge pruning topology optimization utilizes true random weights from resistive memory arrays to initialize overparameterized networks and reduces programming overhead by eliminating redundant connections. Integrated with sparse weight mapping77, this method further minimizes memory footprint (see Supplementary Table 2). This co-design addresses the primary obstacles of programming stochasticity and cost in analog computing, laying the foundation for the next generation of AI hardware with high energy efficiency (see Supplementary Table 6 for edge pruning topology optimization works for other commonly used analog computing devices).

Methods

Fabrication of resistive memory chip

Under the 40 nm technology node, the fabricated resistive memory chip integrates a 512 × 512 crossbar array, with cells formed between the metal-4 and metal-5 layers using a backend-of-line process. Each cell consists of bottom and top electrodes (BE and TE) and a transition-metal-oxide dielectric layer. The BE via (60 nm diameter) is defined by photolithography and etching, filled with TaN by physical vapor deposition, and capped with a 10 nm TaN buffer layer. A 5 nm Ta layer is then deposited and oxidized to form an 8 nm TaOx dielectric layer. The TE is realized by sequential PVD deposition of 3 nm Ta and 40 nm TiN. After cell formation, the remaining interconnect metals are completed using a standard logic process. Cells in the same row share a common BE line, whereas cells in the same column share a common TE line. Following a 30-min post-anneal at 400 °C in vacuum, the 40 nm resistive memory chip exhibits excellent properties, including high yield and robust endurance (see Supplementary Figs. 1,2 for detailed device characteristics).

Hybrid analog-digital hardware system

The hybrid analog-digital hardware system (see Supplementary Fig. 4) comprises a 40 nm resistive memory chip and a Xilinx ZYNQ SoC, which integrates a field-programmable gate array (FPGA) and an ARM processor on a printed circuit board (PCB). The resistive memory chip operates in three modes under the edge-pruning topology optimization scheme: an electroform mode for generating random conductance weights, a reset mode for pruning selected weights, and a multiplication mode for vector-matrix operations. In electroform mode, dielectric breakdown is induced in the resistive memory array to form random conductance matrices: all source lines (SLs) are biased to a fixed programming voltage supplied by an eight-channel 16-bit analog-to-digital converter (DAC, DAC80508, Texas Instruments), while bit lines (BLs) are grounded and word lines (WLs) are biased by the DAC to enforce a compliance current and prevent hard breakdown. The SL voltage amplitude and pulse width tune the post-breakdown conductance distribution and sparsity. In reset mode, selected cells are returned to the off state: the target BL is biased by the DAC, the corresponding SL is grounded, and the remaining SLs are left floating. In multiplication mode, a 4-channel analog multiplexer (CD4051B, Texas Instruments) controlled by an 8-bit shift register (SN74HC595, Texas Instruments) applies DC voltages to the BLs. During each training step, the resistive memory chip is read, and the vector-matrix products, encoded in the SL currents, are converted to voltages by transimpedance amplifiers (OPA4322-Q1, Texas Instruments) and digitized by 14-bit ADCs (ADS8324, Texas Instruments). The resulting data are transferred to the Xilinx SoC for further processing. The FPGA implements the control logic for driving the resistive memory and exchanges data with the ARM processor via direct memory access to DRAM. It also accelerates selected neural network operations in hardware, such as activation and pooling.

Multi-Bit vector-matrix multiplications

To perform vector-matrix multiplication, the analog input vector is first converted into an m-bit binary vector. In this process, each input element is encoded as a binary number with m bits, where m equals 4 for CNN, 3 for CRNN, and 6 for U-Net. The analog multiplication is thus approximated by m successive multiplications using binary input vectors at different significance levels. In each step, a row is biased to a small fixed voltage (e.g., 0.1 V) if the corresponding bit is “1”, and is grounded if the bit is “0”. The resulting column currents are sequentially read out through a column multiplexer. Finally, these currents are scaled by their respective bit significance and summed in the digital domain.

Reset and set operations

Edge pruning topology optimization

The weight pruning process is physically implemented by driving the corresponding resistive-memory differential pairs into the off state via reset operations, while reinstatement is achieved by returning these cells to their conducting states via set operations. The set operation is realized by applying identical pulses with a 3.3 V amplitude and 300 ns width to the BLs of the resistive-memory array, thereby switching pruned cells back to the conducting state and reinserting them into the sub-network. The reset operation is implemented by applying identical pulses with a 2.6 V amplitude and 400 ns width to the SLs, annihilating the conductive filaments and driving the cells into the off state. Importantly, there is a large margin between the off state and the conducting state, so precise conductance programming is unnecessary.

Weight optimization

For weight optimization, identical pulses with a 1.5 V amplitude and 500 ns width are used to program the resistive-memory cells. The programming current is limited by the transistor gate voltage on the WL to control the conductance distribution. Each cell in a differential pair is tuned to its target conductance using a closed-loop write scheme78, followed by write-verify steps that ensure an approximate 10% conductance error margin.

Edge pruning topology optimization algorithm

The edge-pruning topology optimization algorithm consists of forward and backward steps. First, a randomly weighted neural network is initialized on the analog resistive-memory chip, where each weight value also serves as the score of the corresponding edge. In the forward pass, a sub-network is selected by pruning hardware weights whose scores fall below a threshold determined by a predefined sparsity (e.g., a sparsity of 0.5 corresponds to pruning 50% of the weights). The inputs are then fed through this sub-network for forward propagation and loss evaluation. In the backward pass, a general-purpose digital processor computes the gradients of the loss function to update the edge scores while keeping the weight values fixed. The scores are updated using a straight-through gradient estimator63,79:

$${\widetilde{s}}_{ij}={s}_{ij}-\eta \,\frac{\partial L}{\partial {I}_{j}}\,{w}_{ij}{Z}_{i},$$
(1)

where sij and \({\widetilde{s}}_{ij}\) denote the edge scores between the hidden nodes i and j before and after the update, respectively, η is the learning rate, \(\frac{\partial L}{\partial {I}_{j}}\) is the partial derivative of the loss L with respect to the input of node j (Ij), and wijZi is the weighted output of node i. These processes are repeated until a well-performing sub-network is selected from the randomly initialized neural network.

Threshold learning rule

To improve the energy and time efficiency during the training process, we follow Yao’s work80 and use the same threshold learning rule to reduce unnecessary programming of resistive memory.

Edge pruning topology optimization

$$\Delta s=\left\{\begin{array}{ll}\Delta s,& \,{{\rm{if}}}\,\,\left|\Delta s\right|\ge {T}_{s}(t),\\ 0,& \,{{\rm{otherwise}}}\,,\end{array}\right.$$
(2)

where \(\Delta s\) is the edge-score update, and \({T}_{s}\left(t\right)\) is the dynamic threshold updated by the following rule:

$${T}_{s}(t)=\left\{\begin{array}{ll}{T}_{s}^{{{\rm{init}}}},\hfill& \,{{\rm{if}}}\,\,t=0,\\ {T}_{s}(t-1)-\frac{{T}_{s}^{{{\rm{init}}}}-{T}_{s}^{{{\rm{end}}}}}{\alpha },& \,{{\rm{otherwise}}}\,,\end{array}\right.$$
(3)

where \({T}_{s}^{{{\rm{init}}}}\), \({T}_{s}^{{{\rm{end}}}}\), and α represent the pre-designed initial threshold, end threshold, and update step, respectively. When a new best accuracy is achieved, the value of t is increased by 1. This decaying threshold speeds up model convergence and is inspired by the learning-rate decay technique81.

Weight optimization

$$\Delta w=\left\{\begin{array}{ll}\Delta w,& \,{{\rm{if}}}\,\,\left|\Delta w\right|\ge {T}_{w},\\ 0,& \,{{\rm{otherwise}}}\,,\end{array}\right.$$
(4)

where \(\Delta w\) represents the weight update, and Tw denotes the pre-designed threshold constant used to ascertain whether a particular cell requires programming. When Tw equals zero, each cell is programmed during every training step, corresponding to weight optimization with free updates. By increasing the value of Tw, the frequency of cell programming decreases, and weight optimization with limited updates is obtained when its programming count is similar to that in the edge pruning topology optimization.

Details of the experimental neural networks

When running randomly weighted neural networks, the analog resistive-memory in-memory computing chip accelerates the most computationally intensive vector-matrix multiplications, while the remaining max-pooling, normalization, and activation operations are executed on the Xilinx SoC. Training hyperparameters are summarized in Supplementary Data 1–3.

CNN backbone

As shown in Fig. 3a, the 4-layer CNN consists of 2 convolutional (C) layers and 2 fully connected (F) layers. The C1 layer uses kernels of size 64 × 1 × 3 × 3 (out channels × in channels × width × height) and produces 64 × 12 × 12 feature maps. The C2 layer uses kernels of size 16 × 64 × 3 × 3 and generates 16 × 10 × 10 feature maps. These maps are then down-sampled by a max-pooling layer with a 2 × 2 kernel and stride 2. The resulting 16 × 5 × 5 feature maps are flattened into a 400-element vector and fed into the F1 layer. F1 has a weight matrix of size 128 × 400 and reduces the input to a 128-element vector. Finally, this vector is passed to the F2 layer with 10 × 128 weights to produce 10 output probabilities corresponding to the image labels.

CRNN backbone

Spoken digits are first transformed into the frequency domain using mel-frequency cepstral coefficients (MFCCs)72, yielding cepstral feature maps suitable for recognition and classification. As shown in Fig. 4a, these 23 × 15 feature maps are then fed into a 5-layer CRNN comprising 2 convolutional layers, 1 recurrent (R) layer, and 2 fully connected layers. The C1 layer uses kernels of size 64 × 1 × 3 × 2, followed by a max-pooling layer that produces 64 × 11 × 14 feature maps. The C2 layer uses kernels of size 32 × 64 × 3 × 2, followed by a maxpooling layer that outputs 32 × 2 × 8 feature maps. These maps are then passed to the R1 layer:

$$h(t)=\left\{\begin{array}{ll}0,\hfill& \,{{\rm{if}}}\,\,t=0,\\ \tanh \left({w}_{ih}{x}_{t}+{w}_{hh}h(t-1)\right),& \,{{\rm{otherwise}}}\,,\end{array}\right.$$
(5)

where t, h(t), wih, and whh denote the time step, hidden state, input-hidden weights (128 × 32), and hidden-hidden recurrent weights (128 × 128), respectively. The time step increases as the model iterates, and when it reaches 4, the final output of the R1 layer is obtained by

$$\,{{\rm{recurrent\; output}}}\,=\frac{{\sum }_{t=1}^{4}h(t)}{4}.$$
(6)

Subsequently, the recurrent output with 128 elements is fed into the F1 (256 × 128) and F2 (10 × 256) layers to obtain the 10 probability outputs that determine the label of the input spoken digit.

U-Net backbone

As shown in Fig. 5a, the U-Net architecture consists of two main parts: a contracting path (down-sampling layers, D) and an expansive path (up-sampling layers, U). Each down-sampling layer applies two 3 × 3 convolutions, each followed by a rectified linear unit (ReLU) activation, and a 2 × 2 max-pooling operation. This progressively extracts higher-level features from the input, enabling the network to capture critical structures and patterns. Each up-sampling layer consists of a bilinear interpolation step, concatenation with the corresponding cropped feature maps from the contracting path, and two subsequent 3 × 3 convolutions, each followed by ReLU. This design facilitates precise localization and accurate segmentation of objects within the image.

During simulations, retinal blood vessel images of size 584 × 565 pixels are first split into 26,400 overlapping 96 × 96 patches. From these, 6400 patches are randomly selected for training, and the remaining 20,000 patches are used for testing. Each patch is fed into an input convolutional layer with kernel size 32 × 1 × 3 × 3 for initial feature extraction, and the resulting feature maps are processed by four down-sampling layers (D1–D4) and four up-sampling layers (U1–U4) for vessel segmentation. The input channel numbers for D1–D4 are 32, 64, 128, and 256, respectively, and for U1–U4 are 256, 128, 64, and 32. An output convolutional layer with kernel size 2 × 32 × 1 × 1 finally maps the U4 feature maps to segmentation probability maps for each patch. The full segmented image is then reconstructed by concatenating all processed patches.

Image segmentation indicators

To demonstrate the performance of U-Net in the DRIVE image segmentation task, several indicators are evaluated, including true positive rate (TPR), false positive rate (FPR), recall, precision, F1 score (F1), and accuracy, as follows:

$${{\rm{TPR}}}={{\rm{Recall}}}=\frac{{{\rm{TP}}}}{{{\rm{TP}}}+{{\rm{FN}}}},$$
(7)
$${{\rm{FPR}}}=\frac{{{\rm{FP}}}}{{{\rm{TN}}}+{{\rm{FP}}}},$$
(8)
$${{\rm{Precision}}}=\frac{{{\rm{TP}}}}{{{\rm{TP}}}+{{\rm{FP}}}},$$
(9)
$${{\rm{F1}}}=2\times \frac{{{\rm{Precision}}}\times {{\rm{Recall}}}}{{{\rm{Precision}}}+{{\rm{Recall}}}},$$
(10)
$${{\rm{Accuracy}}}=\frac{{{\rm{TP}}}+{{\rm{TN}}}}{{{\rm{TP}}}+{{\rm{FP}}}+{{\rm{TN}}}+{{\rm{FN}}}},$$
(11)

Here, Recall, Precision, F1, and Accuracy are widely used performance metrics for evaluating image segmentation tasks. Recall evaluates the U-Net’s ability to identify all relevant instances, Precision measures the correctness of positive predictions, F1 provides a balanced score ranging from 0 to 1, with higher values representing better classification performance, and Accuracy indicates the proportion of correct predictions made out of the total number of predictions. These metrics help assess classification performance accurately.