Introduction

In practical applications of crystalline silicon solar cells, multiple cells are interconnected and encapsulated within photovoltaic (PV) modules for outdoor deployment. To meet specific output voltage and current design requirements, a PV module typically consists of several cell strings connected in parallel, and a cell string is formed by a number of solar cells connected in series. Partial shading is an inevitable condition in outdoor deployments, occurring when a section of a PV module is obstructed from sunlight, such as when covered by snow, leaves, or dust, or obstructed by buildings, trees, or other structures1,2,3,4. This phenomenon poses a significant challenge for PV modules, as even a small shaded area can lead to disproportionately large reductions in overall power output and even damage to the PV system4,5,6,7. PV modules are primarily affected by partial shading in two primary ways: current mismatch loss and the formation of hot spots.

Current mismatch loss, caused by variations in electrical characteristics or differences in operating conditions among individual cells within a cell string, can lead to reduced power output from the PV module. In the case of shading on a cell within a cell string, the maximum current generated by the shaded cell decreases in proportion to the shading ratio. Since all cells conduct the same current in series-connected configurations, the output of the entire string is limited by the shaded cell. Consequently, total shading of a single cell can lead to a full interruption of current flow from the entire cell string.

A more severe concern is the formation of hot spots. Shaded cells in a string enter reverse bias due to carrier accumulation from the unshaded, actively generating cells. If this reverse bias becomes sufficiently large or persists over an extended period, reverse breakdown could be triggered at the shaded regions or at pre-existing defect sites within the shaded cell. The resulting high reverse breakdown current density in these localized areas can lead to significant overheating, potentially resulting in permanent thermal damage to the PV module or even combustion in extreme cases. The reverse bias effect caused by partial shading is also a significant factor contributing to the stability degradation of perovskite solar cells8,9,10,11. Different regions within a solar cell can be considered electrically analogous to parallel-connected subregions. Under partial shading conditions, although the entire shaded cell is subjected to the same reverse bias, the reverse bending of the energy band in the shaded region is more pronounced than in the unshaded regions within the cell, which is akin to the contrast between a reverse bias diode under illumination and one in the dark state. As a result, the shaded region is more susceptible to reverse breakdown than the unshaded regions within the shaded cell. Furthermore, if the reverse bias becomes excessively large or if heat accumulates, thermal and electrical stress may extend to adjacent regions of the cell.

In terms of a cell string affected by partial shading, if the shaded cell lacks a reverse leakage path, the output current of the entire string becomes severely restricted. Conversely, the presence of reverse leakage paths may lead to the formation of hot spots due to localized heating. Several studies have demonstrated a correlation between solar cells with lower reverse breakdown voltages and improved shading tolerance for output power loss12,13,14. However, cells with low reverse breakdown voltages tend to exhibit lower efficiency under standard operating conditions due to shunting, as reverse current leakage in solar cells typically arises from various recombination or leakage processes, which occur under both reverse and forward bias conditions, posing a challenge in enhancing shading tolerance to output power loss without adversely affecting cell efficiency15,16,17,18. Moreover, it remains unclear whether the hot-spot problem is alleviated. The conventional perception that back-contact (BC) cells inherently possess certain shading tolerance arises from the fact that the positive and negative electrodes are adjacent, making leakage easier. However, this characteristic also degrades the electrical performance of BC cells. High-efficiency BC cells employ insulating layers or increase the spacing to more strictly isolate the positive and negative electrodes, which in turn weakens reverse conduction capability and reduces shading tolerance.

To minimize the impact of partial shading, researchers have developed various external strategies rather than modifications to cell structures, since maintaining high cell efficiency remains a critical priority. The external strategies include alternative cell geometries, specialized cell interconnection schemes, advanced circuit control techniques, etc.4,18,19,20,21,22,23,24 Among these, the most practical approach is the use of external bypass diodes, which involves connecting additional reverse diodes in parallel with the solar cells. These reverse diodes provide an alternate path for current under shading, thereby mitigating current mismatch losses and the formation of hot spots.

The one-bypass-diode-per-cell concept is already commercialized by AE Solar company. However, this method introduces additional cost, increases the complexity of PV module circuitry and reduces packing density to accommodate the bypass diodes. To balance functionality and cost, it is typically not feasible to equip each solar cell with an individual bypass diode in commercial PV modules. Instead, one bypass diode is connected across an entire cell string as a protective measure against hot spots, although this configuration offers limited effectiveness in preserving output power under partial shading conditions25,26,27. The concept of integrating bypass diodes within the cell has been proposed early14,17,18, while the bypass diode is still an additional component, independent from the cell itself, and is essentially no different from the bypass diodes connected at the module level. This concept has the same problems of cost and complexity as the one-bypass-diode-per-cell concept.

These developed strategies increase system complexity and cost, highlighting the need for built-in shading tolerance of PV modules through innovations in structural design of solar cells. The in-cell design represents a trend toward functional integration and system-level optimization at the cell level, serving as a key enabling technology for highly reliable, highly-performance, and low-cost photovoltaic systems.

In this study, we first evaluate the potential of bypass diodes to mitigate issues arising from partial shading. Then we investigate the design of high-efficiency solar cells for shading-tolerant PV modules. The design principles are summarized, and a specific cell structure is proposed. The characteristics of the proposed cell structure are verified through cell-level experiments and simulations. We further elucidate the underlying operating mechanism of the cells, clarify how PV modules maintain functionality under partial shading conditions, and analyze the impact of introduced conduction channels on cell performance. Additionally, we explore a variety of strategies for the cell modulation. The shading tolerance of PV modules incorporating the proposed cells is experimentally validated through comparative analysis.

Results and discussion

Design of solar cells for shading-tolerant modules

Inspired by the bypass diode mechanism described in Supplementary Note 1, we propose a concept of in-cell bypass diodes that involves intentionally introducing spatially uniform reverse conduction channels across the solar cell as illustrated in Fig. 1a. When designing a solar cell structure for shading-tolerant PV modules, the cell should exhibit current density-voltage (J–V) characteristics similar to those of a cell with an external bypass diode connected in parallel, i.e., the cell should possess reverse conduction capability, preferably with a low threshold voltage for reverse conduction. This approach enables the shaded cell to conduct current under reverse bias conditions. Meanwhile, the reverse current should be distributed across multiple reverse conduction channels, thereby effectively mitigating the formation of hot spots caused by excessive localized current. In addition to maintaining cell efficiency, we come up with three key design principles for developing high-efficiency solar cells for shading-tolerant PV modules.

Fig. 1: Design of solar cells for shading-tolerant modules.
Fig. 1: Design of solar cells for shading-tolerant modules.The alternative text for this image may have been generated using AI.
Full size image

a Inspired by the mechanism of bypass diodes, the design of solar cells for shading-tolerant modules requires reverse conduction capability with spatially uniform distribution. b Designed solar cell structure scheme with built-in reverse conduction channels by introducing “n-c-Si/ETL/HTL" stacks near the p-n junction region of a back-contact (BC) solar cell, each gap region of the cell has such a stacked structure can serve as reverse conduction channel. c The dark state current density-voltage (J–V) characteristics of the proposed cell as obtained from experimental measurements and simulations. The dashed lines represent the results for the experimental cell samples, the solid line correspond to the simulated result. d Certified power conversion efficiency (PCE) of a cell with structure proposed in this work. Source data are provided as a Source Data file.

Principle I: The cell should exhibit a spatially uniform distribution of reverse conduction channels. The method described in this work essentially mimics the function of external bypass diodes, namely providing the solar cell with reverse conduction capability. In addition, it is preferable for this reverse conduction path to be uniformly distributed within the cell, with the aim of reducing the overall reverse threshold voltage. This, in turn, leads to lower heat generation. Principle II: The impact of reverse conduction channels on cell efficiency should be minimized. In addition to providing conduction capability when the cell is reverse-biased, the bypass diode must not exhibit leakage when the cell is forward-biased. Otherwise, it would result in an effect similar to parallel resistance reduction, leading to decreased cell efficiency. Principle III: The absolute value of the reverse threshold voltage should be minimized. According to the discussion in Supplementary Note 1 regarding the impact of the bypass diode’s threshold voltage, the smaller the threshold voltage, the better. This gives rise to Principle III. In fact, the multi-channel design described in Principle I serves the same purpose: the more channels there are, the smaller the equivalent threshold voltage becomes. In this context, the reverse threshold voltage is defined as the reverse voltage at which the reverse current equals the current at the maximum power point (MPP) of the cell.

The first principle involves introducing reverse conduction channels into the solar cell. Different types of solar cells can exhibit similar localized stacked regions, which are formed by the contact of carrier-selective transport layers (CTL) for opposite types of charge carriers, the hole-selective transport layer (HTL) and the electron-selective transport layer (ETL). These localized stacks can lead to leakage issues that degrade solar cell efficiency. However, the stacks can also be deliberately engineered to perform specific functions, such as serving as reverse conduction channels. The leakage behavior of these localized stacks varies depending on their stacking orders and locations within the cell. To activate the conduction channel under reverse bias conditions, and based on our earlier studies on the bias-dependent switching behavior of the stacks28, the required stack configuration is “n-c-Si/ETL/HTL” type, and these structures must be positioned on the p-n junction side of the cell. This enables them to function effectively as reverse conduction channels. To achieve spatially uniform distribution of these channels, we consider BC solar cells29,30,31,32. In BC cell architectures, hundreds of transition regions (gap regions), formed between opposite type electrodes, are evenly distributed across the rear surface of the cell. The edges of each gap region can be used to form the required localized stacked structures. As a result, the reverse conduction channels can be nearly uniformly distributed across the entire back surface of the cell.

Taken together, we propose a cell structure scheme as illustrated in Fig. 1b, the minimum repeating unit of the cell structure. The design is derived from silicon heterojunction BC cell architecture31,32, featuring n-type crystalline silicon (n-c-Si) as substrate. The passivation and doping layers for ETL are prepared first, followed by the passivation and doping layers for HTL. During the patterning process, the HTL is intentionally deposited to partially overlap the ETL, thereby forming localized “n-c-Si/ETL/HTL” stacks. Transparent conductive oxide (TCO), typically indium tin oxide (ITO), and metal electrodes, usually silver (Ag), are then applied for charge collection and conduction. In the TCO patterning step, part of the p-region TCO is also deliberately deposited on the “n-c-Si/ETL/HTL” stacks, thereby introducing the stacks into the cell from the p-n junction side, in accordance with the proposed structural design requirements.

Sample fabrication and device simulations were conducted according to the solar cell structure scheme illustrated in Fig. 1b. Figure 1c presents the dark state J–V characteristics of the proposed cell as obtained from experimental measurements and simulations. The red solid line corresponds to the simulated result, the other lines represent the results for the experimental cell samples. By adjusting the patterning template of TCO, the proportion of localized stacked structures introduced to the total circuit can be modified. The p-region TCO of cell sample e0 is not covered on the stacked structures, and cell sample e1 exhibits a higher proportion of introduced stacked structures compared to sample e2. The results demonstrate that the cells incorporating the localized stacked structure exhibit reverse conduction behavior comparable to that of a cell incorporating an external bypass diode.

Notably, both cell sample e1 and sample e2 maintain high efficiency, with no significant efficiency loss compared to the cell e0. This indicates that the introducing of reverse conduction channels does not compromise cell efficiency under forward bias condition. A certified power conversion efficiency(PCE) of 27.49% was achieved for a solar cell featuring the structure proposed in this work, as shown in Fig. 1d. This observation stands in contrast to previous studies, which suggest that increased reverse current leads to a reduction in solar cell performance15,16,17,18. The discrepancy likely arises from fundamental differences in the nature of the engineered reverse conduction channels employed in this work.

Reverse current formation

To elucidate the mechanism by which the proposed solar cell conducts current under reverse bias, the carrier transport process at the cell scale was analyzed using device simulation. The current flow information under reverse bias conditions is shown in Fig. 2a. The color mapping represents the magnitude of local current density, the length and orientation of the arrows indicate the magnitude and direction of current density at each arrowhead location. In contrast to conventional cells, which exhibit negligible conduction under reverse bias, the proposed cell demonstrates a substantial current density distribution within the silicon substrate. The current originates from the n-region of the cell and subsequently flows toward the edge of the gap region adjacent to the p-type region (Fig. 2a(ii)). Within this region, current density above the p-region is minimal due to the junction formed by HTL in the silicon substrate, which impedes carrier flow. Consequently, the current in the substrate is eventually redirected to the edge of the gap region, where the localized “n-c-Si/ETL/HTL” stacked structure is located (Fig. 2a(iii)).

Fig. 2: Operating mechanisms of the solar cell.
Fig. 2: Operating mechanisms of the solar cell.The alternative text for this image may have been generated using AI.
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a Current flow in the designed solar cell under reverse bias conditions. The color mapping represents the magnitude of local current density, the length and orientation of the arrows indicate the magnitude and direction of current density at each arrowhead location. b Current distribution around the stacked region under reverse bias condition of the cell, with the color mapping indicating the magnitude of current density at each corresponding location: (i) total current distribution with labeled representative spatial transport paths; (ii) spatial distribution of electron current; (iii) spatial distribution of hole current. c Schematic diagram of the energy band structure of the stacked region under (i) reverse bias and (ii) forward bias conditions. d A detailed equivalent circuit diagram representing the essential transport processes of reverse current. Several different band-to-band tunneling (BTBT) processes of “electronic current → hole current" are indicated by Esaki-like diodes in the corresponding locations. The BTBT processes of “hole current → electronic current" are omitted here to highlight the main focus. e The role of the stacked region as built-in reverse conduction channels within individual cells in a cell string circuit. Source data are provided as a Source Data file.

Zooming into this region reveals the detailed layer structure and corresponding current information, as illustrated in Fig. 2b(i). By decomposing the total current density into electron current density (Fig. 2b(ii)) and hole current density (Fig. 2b(iii)), it is evident that the current undergoes a sequential transformation process of “electron current → hole current → electron current” when passing through this region. Specifically, the electron current in the substrate and the ETL is converted into hole current within the HTL and a thin underlying silicon layer, which is attributed to the formation of the HTL-induced hole inversion layer (p+-c-Si) in this thin layer. The resulting hole current is subsequently converted into electron current within the p-region TCO and eventually collected by the electrode.

During this process, the carrier flow undergoes two band-to-band tunneling (BTBT) transitions, corresponding to the aforementioned two current-type conversions, as shown in Fig. 2b. The ETL/HTL stacked structure facilitates the first BTBT process (electron to hole conversion). This is due to the narrow depletion region at the ETL/HTL interface, which is in contrast to the wide depletion region at the n-c-Si/HTL interface that inhibits reverse BTBT process, this narrow depletion region forms a localized energy band configuration resembling an Esaki diode, enabling BTBT to occur at relatively low reverse bias voltages, as depicted in Fig. 2c(i).

Reverse current distribution

From the perspective of mitigating hot-spot formation, it is essential to analyze not only the existence of reverse current but also its spatial distribution. Specifically, this involves evaluating the locations where the two current-type conversions occur by examining the lateral transport processes of carriers at the device level.

In this context, the lateral conduction capability of the amorphous silicon (a-Si) thin layers is considered negligible. The electrical conductivity of a-Si primarily arises from carrier transitions in localized and extended states. Due to its inherently disordered atomic structure and high density of defect states, the carrier mobility in a-Si remains much lower than that in crystalline silicon (c-Si)33,34, even after hydrogen passivation35,36,37. Furthermore, the a-Si layer is typically only several tens of nanometers thick, which exacerbates interfacial scattering effects and further restricts lateral conduction. This limitation also underpins the necessity of employing TCO layers to facilitate lateral carrier collection in silicon heterojunction solar cells.

Based on differences in carrier lateral transport mechanisms, the reverse current flow in the proposed cell can be categorized into three fundamental transport pathways, as illustrated in Fig. 2b(i). Path A: Two current-type conversions occur early, the resulting electron current is then laterally transported through TCO to the edge of the gap region, then to the p-region electrode. Path B: The electron current is laterally transported through the c-Si substrate to the edge of the gap region, where the two current-type conversions occur, the resulting electron is then conducted laterally through TCO to the p-region electrode. Path C: The electron current is laterally transported through the n-c-Si substrate to the edge of the gap region, then the first current-type conversion occurs, followed by lateral conduction through the HTL-induced p+-c-Si inversion layer. After that, the second current-type conversion occurs before the resulting electron current flows vertically to the p-region electrode.

A detailed equivalent circuit diagram representing the essential transport processes of reverse current is shown in Fig. 2d. Regardless of the dominant pathway, the overall effect of the stacked region is functionally analogous to introducing Esaki-like diodes in parallel with the primary p-n junction diode of the solar cell (Fig. 2e). It is desirable for Path A to dominate the reverse conduction process, as the current flow of Path A is distributed across the localized stacked region. In contrast, current flow through Paths B and Path C concentrates near the edge of the gap region, potentially leading to localized heating and an increased risk of hot-spot formation.

In practical cell fabrication, the edge of the stacked regions may not exhibit the same precision as modeled in device simulations. Limitations inherent to the patterning process, such as imprecise edge morphology, non-uniform layer thickness, variability in interfacial properties, and the possible formation of defect-rich regions, can lead to uncontrollable cell performance. If a defect-rich region forms at the edge, the reverse current may become concentrated there, leading to overheating problem and reduced cell efficiency due to recombination and leakage through the defect. To ensure the reliability and stability of the fabrication process, electrical insulation of the edge regions is recommended. This approach helps mitigate the impact of edge-related uncertainties and ensures the reverse current is primarily transported through the intended stacked structure.

Forward bias behavior

The localized “n-c-Si/ETL/HTL" stack formed near the p-region of the cell behaves similar to an Esaki diode, and shares the same bias state as the overall cell device. Therefore, when the cell operates under forward bias condition, the localized stack also operates in forward bias state based on the description as an Esaki-like diode.

There are two types of current in the forward bias state of the localized stack: diffusion current and tunneling current. The diffusion current increases gradually with increasing forward bias voltage, following a trend consistent with the diffusion current in the p-n junction region of the cell, both can be regarded as the majority carrier diffusion from n-c-Si to HTL. The tunneling current, on the other hand, arises from the reverse conduction channels that remain active even under forward bias. As the cell forward bias increases, these tunneling conduction channels at the ETL/HTL interface of the stacked region gradually close (Fig. 2c(ii)).

If the current passing through the stacked region is considerable large at the MPP voltage of the cell, the stacked region may adversely affect overall cell efficiency. Ideally, if the threshold voltage of the diffusion current in the stacked region is greater than that of the diffusion current in the cell p-n junction region, and the tunneling conduction channels in the stacked region are effectively closed prior to reaching the MPP voltage of the cell, the stacked region would not degrade cell performance. The magnitude of the diffusion current and tunneling current through the stacked region, as well as the closure of the tunneling channels, depends on the properties of HTL, ETL and interface in-between, which are the factors that govern the modulation strategies for conduction channels in the stacked region, a detailed analysis is provided in Supplementary Note 2.

Although a single modulation approach cannot simultaneously satisfy both Principle II and Principle III, The current through the stacked region, unlike leakage currents caused by poor shunt resistance, can be effectively modulated through various means. The key is to ensure that the tunneling current through the stacked region predominantly occurs via BTBT process, while minimizing trap-assisted tunneling (TAT), thereby reducing its negative impact on cell efficiency. In practical applications, there is no requirement for an excessively large reverse current in the shaded cell. A portion of the BTBT conductivity can be deliberately sacrificed through modulation methods, while simultaneously suppressing the TAT conductivity. This ensures that the cell retains sufficient reverse conduction capability without compromising efficiency.

In a word, the difference between a conventional BC cell and the BC cell proposed in this study lies primarily in their conduction behavior. The reverse current pathways in conventional BC cells can be regarded as leakage, which exists under both forward and reverse bias and consequently degrades cell efficiency. In contrast, in the proposed design, reverse conduction occurs through stacked-layer channels, which exhibit an Esaki-diode-like behavior. Our approach leverages the reverse conduction capability of the Esaki-like structure. Under forward bias, as long as the current flowing through the stacked layers near the MPP does not exceed the diffusion current of the p-n junction region, the cell efficiency remains unaffected. The forward current in the stacked layers consists of both diffusion and tunneling components. The band structure ensures that the diffusion current within the stacked layers does not exceed that of the p-n junction region, while the tunneling current becomes the dominant factor requiring careful consideration. The magnitude of the tunneling current is governed by the applied voltage and the conductivity of the tunneling channel, which itself varies with the applied voltage, gradually increasing under reverse bias and decreasing under forward bias.

Validation and comparison of PV modules

PV modules fabricated using the proposed cells were evaluated under partial shading conditions and compared with baseline modules composed of cells lacking engineered reverse conduction channels. The modules consist of 6 cell strings, connected in a 3-series by 2-parallel configuration, with each cell string comprising 24 half-size cells (182 mm × 91 mm). In the baseline modules, each pair of parallel-connected cell strings is equipped with a shared bypass diode.

The hot-spot test compares the peak temperature, heat distribution, and electroluminescence (EL) characteristics between the baseline module and the module developed in this work, based on the international standard “IEC 61215-2:2021” established by the International Electrotechnical Commission (IEC), which is designed to evaluate the module’s resistance to hot-spot formation under extreme conditions. The baseline modules exhibited much higher temperature in the shaded region, stabilized at around 190 °C after a period of shading. In contrast, the temperature in the modules developed in this work was stabilized at around 90 °C (Fig. 3a). Infrared thermal imaging revealed more concentrated heat accumulation in the baseline modules, along with the formation of several permanent heat-damaged spots observed in the EL measurements, compared with the proposed modules in this work (Fig. 3b).

Fig. 3: Validation and comparison of PV modules.
Fig. 3: Validation and comparison of PV modules.The alternative text for this image may have been generated using AI.
Full size image

a, b Hot-spot test compares the peak temperature, heat distribution and electroluminescence (EL) characteristics between the baseline module and the module developed in this work. c, d Comparison of the output stability under small-area partial shading conditions by shading one cell with different shading ratio. e–g Comparison of the operating temperature under various partial shading conditions between the baseline module and the proposed module. Source data are provided as a Source Data file.

Furthermore, to validate the advantage in module power output stability performance under small-area partial shading, the maximum power (\({P}_{\max }\)) degradation was evaluated by shading one cell with various shading ratios in the modules. The power output of the baseline module declined proportionally with increased shading, with complete shading of a single cell resulting in a loss of nearly half of the power output due to reduction in current (Fig. 3c). The continuous decline in \({P}_{\max }\) indicates that the installed external bypass diodes have minimal effect on power output stabilization, serving more as a protective component under high current conditions (short-circuit current density Jsc remains unchanged). By contrast, the module in this work demonstrated significantly improved resilient to partial shading, showing only a limited reduction in power output (Fig. 3d). This result is consistent with the trending presented in Supplementary Fig. 2f. Of course, when the shaded area of a PV module becomes excessively large, the effect on output stability becomes less pronounced. In such cases, the primary issue to address is reducing the shading itself. Figure 3e–g present a comparison of module operating temperatures under commonly encountered large-area shading in different forms. The external testing conditions are similar to those of the hot-spot test, with the difference that the temperature control targets the internal LID box temperature at 50 °C rather than the module temperature. The proposed modules in this work exhibit the advantage of lower operating temperatures under all these shading conditions, particularly under commonly encountered short-side shading.

To sum up, the module composed of the proposed cells in this work exhibits clear advantages in thermal management and power output stability under partial shading conditions. The design principles, conduction channel introduction mechanism, and modulation strategies in this work may also provide valuable insights for BC solar cells based on other passivating-contact schemes38. The in-cell design approach demonstrates application potential in PV devices by reducing cost, improving reliability, and enabling integration of system-level functionalities. With continued advances in materials science and manufacturing technologies, this approach is expected to become an important direction for future PV technology development.

Methods

Cell fabrication

Solar cells were fabricated on LONGi commercial research and development line for BC cells. Half-size LONGi M10 n-type Czochralski monocrystalline silicon wafers in (100) orientation, with a resistivity of 8 Ω cm to 12 Ω cm and a thickness of 140 μm, were used as substrate. The front wafer surface was textured and capped with AlOx/SiNx stack to minimize the front surface recombination and the light reflection. Rear side passivation contact was done by HTL (intrinsic hydrogenated amorphous silicon layer deposition followed by p-type hydrogenated amorphous silicon layer deposition) using plasma-enhanced chemical vapor deposition, and ETL (tunnel oxide layer preparation followed by n-type poly silicon deposition) using thermal oxidation and lower pressure chemical vapor deposition. The HTL and ETL layers on the rear surface were interdigitate-patterned through laser patterning during the preparation process. The patterned TCO layers were deposited via magnetron sputtering using indium tin oxide (ITO) as the target material. Silver paste was screen-printed and fired afterwards for metallization. Details about laser patterning can be found in Wu et al. work31 and Wang et al. work32.

Characterization

The current-voltage characteristics in Fig. 1d were measured and certified by ISFH. The current-voltage characteristics of other samples were measured using a Sinton FCT-650 tester under standard test condition (AM1.5G, 1000 W m−2 and 25 °C). The hot-spot tests were conduct indoor in a Light-Induced Degradation (LID) test chamber, under 1 sun irradiance (about 1060 W m−2), 6 cells were shaded in each panel (the weakest six cells in each string, the six cells with the highest temperature in each cell string was identified in the preliminary unshaded temperature test using infrared thermometers), the temperature of the unshaded area of the module is controlled at 55 °C, and the panels are in the short-circuit state. The PV module temperature measurements were conducted through thermocouples on the back side of the shaded region (Fig. 3a, e–g).

Device simulation

The simulated result in Fig. 1c, the current distribution and direction in Fig. 2a, and the band diagrams in Fig. 2c were obtained from the device simulation of a complete BC structure with passivation layers, doped layers, TCO layers and contacts as shown in Fig. 1b. The device simulation in this work was performed by TCAD based on drift-diffusion models with the tunneling process using the nonlocal tunneling model, and tunneling probabilities were calculated using the Wenzel-Kramers-Brillouin approximation. Both trap-assisted tunneling and band-to-band tunneling models were considered at the ETL/HTL interface.

Reporting summary

Further information on research design is available in the Nature Portfolio Reporting Summary linked to this article.