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Ferroelectric transistors for low-power NAND flash memory

Nature volume 648, pages 320–326 (2025)Cite this article

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Abstract

NAND flash memory is essential in modern storage technology, amid growing demands for low-power operation fuelled by data-centric computing and artificial intelligence1,2. Its unique ‘string’ architecture3, where multiple cells are connected in series, requires high-voltage pass operation that causes a large amount of undesired power consumption4. Lowering the pass voltage, however, poses a challenge: it leads to an associated reduction in the memory window, restricting the multi-level operation capability. Here, with a gate stack composed of zirconium-doped hafnia and an oxide semiconductor channel, we report ultralow-power ferroelectric field-effect transistors (FeFETs) that resolve this dilemma. Our FeFETs secure up to 5-bit per cell multi-level capability, which is on par with or even exceeds current NAND technology, while showing nearly zero pass voltage, saving up to 96% power in string-level operations over conventional counterparts. Three-dimensional integration of FeFET stacks into vertical structures with a 25-nm short channel preserves robust electrical properties and highlights low-pass-voltage string operation in scaled dimensions. Our work paves the way for next-generation storage memory with enhanced capacity, power efficiency and reliability.

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Fig. 1: Pathway to optimize power efficiency for ultralow-power FeNAND.
Fig. 2: Memory operation and pass disturbance characteristics.
Fig. 3: Enhanced memory window and multi-bit operation capability.
Fig. 4: Implementation in 3D structure.

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Data availability

The data that support the findings of this study are available from the corresponding authors upon request.

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Acknowledgements

We gratefully acknowledge the support provided by the staff of SAIT’s 200-mm line.

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Authors and Affiliations

  1. Thin Film Technical Unit, Device Research Center, Samsung Advanced Institute of Technology (SAIT), Samsung Electronics, Suwon, Korea

    Sijung Yoo, Taek Jung Kim, Seung-Geol Nam, Donghoon Kim, Kihong Kim, Yunseong Lee, Moonil Jung, Kwang-Hee Lee, Seokhoon Choi, Seung Dam Hyun, Min-Hyun Lee, Seogwoo Hong, Haesung Kim, Ki Deok Bae, Sanghyun Jo, Yoonsang Park, Kyung Mee Song, Kyooho Jung, Jee-Eun Yang, Seung-Yeul Yang, Sangwook Kim, Jinseong Heo & Duk-Hyun Choe

  2. Analytical Engineering Group, Material Research Center, Samsung Advanced Institute of Technology (SAIT), Samsung Electronics, Suwon, Korea

    Hyangsook Lee, Jung Yeon Won, Dong-Jin Yun & Byeong Gyu Chae

  3. Semiconductor Research and Development Center, Samsung Electronics, Hwaseong, Korea

    Wook Ghee Hahn, Chang Hyun Joo, Suhwan Lim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim & Daewon Ha

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Contributions

S.Y. designed the research and conducted the electrical measurements and TCAD simulations. T.J.K. and D.-H.C. developed the in-house numerical simulator and carried out the numerical simulations. S.Y., S.-G.N., D.K., Y.L., M.J., K.-H.L., S.C., S.D.H., M.-H.L., S.H., H.K. and K.D.B. designed and optimized the device fabrication process. Kihong Kim performed the X-ray diffraction measurements. H.L. performed the transmission electron microscopy measurements. J.Y.W., D.Y. and B.G.C., performed the chemical analysis. W.G.H., C.H.J., S.J., Y.P., K.M.S., K.J., S.L., K.S., Kwangsoo Kim, W.K. and D.H. contributed to the discussion and revision of the paper. J.-E.Y., S.-Y.Y., S.K., J.H. and D.-H.C. supervised the project. S.Y. and D.-H.C. co-wrote the paper.

Corresponding authors

Correspondence to Sangwook Kim or Duk-Hyun Choe.

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Nature thanks Jiezhi Chen, Asif Khan, Kai Ni and the other, anonymous, reviewer(s) for their contribution to the peer review of this work. Peer reviewer reports are available.

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Extended data figures and tables

Extended Data Fig. 1 Numerical simulation of PGM and ERS characteristics.

a, Evolution of Vth, extracted internal charge density parameters, and electric field captured at 1 μs PGM operation. b, Evolution of Vth, extracted internal charge density parameters, and electric field captured at 10 ms ERS operation. During the ISPP operation, unhindered polarization switching and charge injection facilitate a substantial Vth shift toward the negative direction as the PGM voltage increases. In contrast, during the ISPE operation, the polarization and trapped charge density are constrained to zero upon switching to the ERS state and remain unchanged even at elevated ERS voltages. c, Electric field applied to the gate IL during the PGM / ERS operation. Notably, for the ERS operation, depletion and floating of the channel limit the voltage drop across the gate stack, resulting in a saturated electric field across the gate IL and negligible electron injection. d, Band diagram captured at 15 V, 1 μs PGM operation. e, Band diagram captured at −11 V, 10 ms ERS operation.

Extended Data Fig. 2 Necessity of the channel IL and its impact on the device characteristics.

a, Electric field applied to the ferroelectric layer at the threshold condition. Solid line indicates the coercive field of conventional hafnia-based ferroelectric materials. b, TCAD simulation results for read operation without channel IL (uncompensated ratio = 1). c, TCAD simulation results for read operation with high-k IL (uncompensated ratio = 0.5). d, Read-after-write-delay characteristics of the device incorporating a 3-nm-thick SiO2 layer. e, SIMS analysis comparing oxygen distribution at the HZO / IGZO interface. f, Transfer curve and memory characteristics of the device with (the proposed structure in this study) and without a Ta2O5 channel IL.

Extended Data Fig. 3 Structure analysis of the fabricated device.

a, Schematic structure and detailed process flow of device fabrication. b, High-angle annular dark-field scanning transmission electron microscopy image of the fabricated device. c, EDS mapping results for the device stack. d, Detailed stack configuration and sample preparation process for XRD measurements. Samples 1 and 2 were fabricated to investigate the role of the metal stressor, and sample 3 was designed to examine the influence of the channel IL on the crystallinity of the HZO film. e, XRD results for the device stack. f, Extracted relative portions of the o/t and m phases. A comparison between samples 1 and 2 highlights the critical role of the metal stressor in promoting the ferroelectric phase, because its absence results in a dominant m-phase. Conversely, the results for sample 3 indicate that the deposition of the Ta2O5 IL has no discernible effect on the crystallinity of the HZO film.

Extended Data Fig. 4 Negative read disturbance characteristics of the device incorporating a 3-nm-thick SiO2 gate IL.

a, Disturbance observed under consecutive read pulses of −8 V with a pulse width of 10 μs b, Disturbance observed under consecutive read pulses of −8 V with 5 μs. The dashed line indicates the predicted maximum number of read operations for a single cell.

Extended Data Fig. 5 Electrical characteristics of the Si FeFET for comparison.

a, Typical memory characteristics of the Si FeFET. b, c, Disturbance characteristics of the Si FeFET showing the threshold voltage variation under accumulated disturbance stress.

Extended Data Fig. 6 Pass disturbance characteristics at elevated temperature (85 °C).

a, b, Pass disturbance characteristics of the device incorporating a 3-nm-thick SiO2 layer. c, d, Pass disturbance characteristics of the device incorporating a 5-nm-thick SiO2 layer. e, Measurement scheme for pass disturbance of the 3D device. f, g, Pass disturbance characteristics of the 3D device.

Extended Data Fig. 7 Numerical simulation for the analysis of relationship between the memory window and PGM voltage.

a, Simulated PGM operation with varying gate IL thicknesses, which is in good agreement with the measured data (Fig. 3b). b, Extracted P, Qit, and Qit′ from the numerical simulation demonstrating that the relationship between memory window and PGM voltage arises from the reduced capacitance of gate IL, which enhances the memory window at a given P, Qit, and Qit′ while requires higher voltage to achieve the same values via charge tunnelling.

Extended Data Fig. 8 ISPP characteristics of 100 devices incorporating a 5-nm-thick SiO2 for Vth distribution evaluation.

The incremental step for the ISPP operation is 0.1 V. The delay between PGM and verify operation was 100 μs. The read-after-write-delay characteristics of our device (Extended Data Fig. 2d) confirm that data stability remains unaffected irrespective of the duration between PGM and verify operation. The ERS state is defined as Vth after an ERS operation, corresponding to the topmost Vth distribution marked with a red dotted line. A total of 31 verification voltages are defined at equally spaced intervals. The subsequent 31 states are determined by their respective verification voltages, where the Vth state that first exceeds the nth verification voltage is designated as the nth state.

Extended Data Fig. 9 Reliability characteristics of the device incorporating a 5-nm-thick SiO2 layer.

a, Retention characteristics of ERS, PGM and intermediate states measured at 25 °C, and b, 85 °C. Each state was achieved using a pulse condition based on the ERS and PGM operation shown in Fig. 2. The memory window slightly increases over time at 85 °C. Although this is not ideal, it is a more favourable behaviour compared to memory window degradation. Importantly, this expansion does not lead to overlap between logical states, which would otherwise compromise data integrity. c, Endurance characteristics measured at 25 °C with QLC-level operation condition (memory window > 6.5 V) and d, PLC-level operation condition (memory window > 11 V). e, Endurance characteristics measured at 85 °C with QLC-level operation condition (memory window > 6.5 V) and f, PLC-level operation condition (memory window > 11 V).

Extended Data Fig. 10 Numerical simulator framework.

a, Workflow of the numerical simulator. b, c, d, Simulated data which are in accordance with the measured data presented in Fig. 2.

Supplementary information

Supplementary Information (download PDF )

This Supplementary Information file contains Supplementary Table 1 and References. Supplementary Table 1: Benchmark comparison of charge-trap-based NAND flash and reported ferroelectric NAND devices, including this work.

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Yoo, S., Kim, T.J., Nam, SG. et al. Ferroelectric transistors for low-power NAND flash memory. Nature 648, 320–326 (2025). https://doi.org/10.1038/s41586-025-09793-3

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  • DOI: https://doi.org/10.1038/s41586-025-09793-3

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