Electrothermal co-optimization of 2.5D power distribution network with TTSV cooling

Abstract

Thermal and power integrity management remains a fundamental challenge in 2.5-dimensional (2.5D) integrated microsystem design. This paper proposes an electrothermal co-optimization design methodology for a 2.5D power distribution network with thermal through silicon via (TTSV) cooling. A hybrid metaheuristic optimization algorithm is presented to optimize the multi-objective function in terms of both the electrothermal properties and manufacturing cost. The proposed approach achieves an optimal solution (minimum fitness value = 310.3) for TTSV scaling and chiplet placement, albeit with increased computational complexity. Compared to the finite element simulation results, the average absolute errors of the impedance and temperature values obtained from the optimization are 3.97$\%$ and 0.35$\%$, respectively. The proposed method is effective in enhancing thermal management, satisfying power and signal integrity requirements, and minimizing manufacturing costs.

Introduction

Two-dimensional semi-integrated circuit (2.5D IC) technology has emerged as an intermediate solution between conventional two-dimensional (2D) and three-dimensional (3D) ICs, combining their respective advantages¹. While 3D ICs offer superior integration density with reduced interconnect latency and power consumption², the stacked architecture leads to significant heat concentration, potentially increasing thermal stress and compromising system reliability³. The 2.5D IC approach addresses these challenges through interposer and redistribution layer (RDL) integration, enabling higher-density packaging while improving thermal management^4,5,6. Unlike 3D ICs, the 2.5D configuration provides more efficient heat dissipation through the interposer and RDL, which serve dual roles as signal transmission pathways and thermal conduits. This architecture also offers greater design flexibility for chiplet customization, facilitating application-specific optimization and future technology upgrades. With these advantages, 2.5D IC technology represents a promising direction for sustainable IC development and a critical enabler of next-generation electronic systems.

Alarmingly, as chiplets achieve higher power consumption and operating frequencies, the electrothermal performance of 2.5D integrated systems faces growing challenges. Simultaneous switching noise (SSN) propagates through the power distribution network (PDN), where power supply noise fluctuations disrupt active circuits, compromising signal and power integrity. Consequently, a robust PDN is critical. Previous studies have investigated PDN impedance characteristics and noise reduction strategies through detailed electrical modeling^7,8,9,10. However, increasing power dissipation also raises temperatures, exacerbating interconnect parasitic effects such as resistivity variations¹¹. Thus, reliable PDN design requires electrothermal co-simulation to precisely predict voltage fluctuations and maintain power integrity. While recent work has enabled fast and accurate PDN modeling^{12,13,14,15,16,17}, electrothermal optimization of PDNs remains underexplored.

Effective thermal management through optimized heat dissipation pathways is crucial for enhancing the electrothermal performance of 2.5D integrated circuits. In contemporary flip-chip packaging architectures, the dominant thermal conduction path typically involves heat transfer from the active junction through the device layer to the chiplet’s backside, ultimately reaching the heat sink and fan assembly. When relying solely on natural convection in the absence of active cooling, the limited heat transfer coefficient of (5–6 W/m²K) leads to substantially increased thermal resistance between the chiplet and its ambient environment, resulting in elevated operating temperatures. Recent advancements in thermal management for 2.5D heterogeneous integration include the development of microchannel-enhanced interposers¹⁸, where embedded microchannel heatsinks establish auxiliary heat dissipation pathways. While this approach improves thermal performance, its practical implementation faces considerable challenges due to manufacturing complexity and the requirement for specialized dielectric cooling fluids¹⁹. An alternative solution emerges in thermal through-silicon via (TTSV) technology, which utilizes high thermal conductivity materials to effectively extract heat directly through the chiplet substrate, thereby significantly reducing thermal resistance^20,21.

The selection of optimization algorithms critically impacts electrothermal design efficiency. Metaheuristic optimization algorithms are widely used for the optimization of circuit designs. For example, particle swarm algorithms (PSO) have been applied to the design of the TSV array for thermal management²². The simulated annealing (SA) is applied to minimize the total cost of decoupling capacitors under the noise constraint²³. A comprehensive comparative analysis of computational intelligence techniques, including PSO, SA, differential evolution (DE), and others are presented for optimal selection and placement of decoupling capacitors in PDNs²⁴. Results show that a single metaheuristic algorithm has some shortcomings. For example, PSO offers rapid convergence and implementation simplicity but tends to converge prematurely to local optima. SA can escape local optima through its Metropolis criterion, albeit with slower convergence rates. DE demonstrates strong global search capability, yet may suffer from premature convergence. To overcome these individual limitations, hybrid algorithms combining complementary strengths have emerged as an effective solution. A novel hybrid optimization algorithm is introduced that synergistically combines moth-flame optimization (MFO) and PSO for accurate transmission line parameter estimation. This innovative approach systematically integrates the fundamental principles of both MFO and PSO to create a robust optimization framework that effectively compensates for their limitations while enhancing overall global search capabilities²⁵. Although the hybrid algorithm introduces higher computational complexity and longer runtime, it achieves significantly improved solution quality, yielding results that are closer to the global optimum. Therefore, the development of hybrid optimization strategies remains a valuable and promising research direction.

This paper focuses on optimizing chiplet PDN design through TTSV heat dissipation. A hybrid metaheuristic optimization (HMO) algorithm is presented to optimize the multi-objective function in terms of both the electrothermal properties and manufacturing cost. The primary contributions of this paper can be summarized as follows:

• The electrical and thermal characteristics of the 2.5D PDN are separately investigated through equivalent circuit modeling and FVM analysis respectively.

• An advanced thermal management strategy employing TTSVs is implemented for high-power chiplets in 2.5D integrated circuits.

• A novel electrothermal co-optimization algorithm is developed to quickly obtain the optimal solution during the optimization process.

• Optimized TTSV pitch distribution and chiplet placement configuration are derived to achieve an optimal trade-off between electrothermal performance and manufacturing cost.

The rest of this paper is organized as follows. Section 2 provides a detailed electrothermal model for 2.5 PDN. An intelligent design method for TTSV cooling is carried out in Section 3. Based on the optimization method, verification and discussion of a 2.5D PDN are executed in Section 4. Finally, a conclusion is drawn in Section 5.

Electrothermal modeling of PDN

Electral modeling

Figure 1 presents a conceptual diagram of an advanced 2.5D integrated circuit design, where an interposer assembles multiple chiplets with different functions to enhance system performance and integration density. This innovative design incorporates a complex PDN to power the different chiplets. Fig. 2 illustrates the electrical modeling of the 2.5D PDN components, a well-established methodology for accurately simulating the electrical characteristics of high-frequency and high-speed circuits. The interposer and chiplet PDN are structured as a grid of power/ground metal wires, which are finely divided into periodically repeating unit cells. Each unit cell in the interposer and chiplet PDN is modeled as a combined resistor-inductor-conductor-capacitor (RLGC) network to capture the fundamental electrical properties and simplify circuit representation for efficient simulation and analysis. These RLGC values of PDNs are calculated using the specified formula as (1)²⁶.

Fig. 1

Example of a 2.5-D PDN. (a) section view, (b) top view.

Fig. 2

The equivalent circuit of the unit cell of (a) interposer PDN and chiplet PDN, and (b) TSVs and bumps.

$$\begin{aligned} {R_{PDN,chiplet}}= (2{P_{1,2}} - {W_{1,2}}){R_{CMS1,2}} + {W_{1,2}}{R_{Micro1,2}} \end{aligned}$$

(1a)

$$\begin{aligned} {L_{PDN,chiplet}}= (2{P_{1,2}} - {W_{1,2}}){L_{CMS1,2}}+ {W_{1,2}}{L_{Micro1,2}} \end{aligned}$$

(1b)

$$\begin{aligned} {C_{PDN,chiplet}}= 2(2{P_{1,2}} - {W_{1,2}}){C_{CMS1,2}}+ 2{W_{1,2}}{C_{Micro1,2}} \end{aligned}$$

(1c)

$$\begin{aligned} {G_{PDN,chiplet}}&= 2\pi f{C_{PDN,chiplet}}\tan (\delta ) \end{aligned}$$

(1d)

where P and W are the pitch and width of the metal grid. Parameters with subscripts of CMS and Micro represent parameters per unit length in the coplanar multistrip type transmission line and the conductor-backed coplanar multistrip type transmission line, respectively. Parameters with subscripts of 1 and 2 represent interposer and chiplet PDN, respectively.

To effectively suppress SSN, metal-insulator-metal (MIM) capacitors with high dielectric constants are integrated into the interposer PDN to enhance the effective capacitance in the unit cells. The MIM capacitors can be configured with values ranging from 0 to 100 pF, allowing flexibility to fine-tune capacitance based on specific performance requirements. Additionally, the design leverages advanced $\mu$-bump and TSV techniques, which are critical for vertical interconnections in 2.5D IC designs, enabling high-density and high-performance integration of the chiplets. The modeling process of TSVs and bumps is detailed in the existing reference²⁷. The modeling parameters of TSV and bump are calculated as (2).

$$\begin{aligned} {R_{TSV}}&= \sqrt{{{\left( {{R_{dc,TSV}}} \right) }^2} + {{\left( {{R_{ac,TSV}}} \right) }^2}} \end{aligned}$$

(2a)

$$\begin{aligned} {R_{bump}}&= \sqrt{{{\left( {{R_{dc,bump}}} \right) }^2} + {{\left( {{R_{ac,bump}}} \right) }^2}} \end{aligned}$$

(2b)

$$\begin{aligned} {L_{TSV}}&= \frac{1}{2}\left( {\frac{{{\mu _0}{\mu _{r,TSV}}}}{{2\pi }}{H_{TSV}}\ln \left( {\frac{{{P_{TSV}}}}{{{r_{TSV}}}}} \right) } \right) \end{aligned}$$

(2c)

$$\begin{aligned} {L_{bump}}&= \frac{1}{2}\left( {\frac{{{\mu _0}{\mu _{r,bump}}}}{{2\pi }}{H_{bump}}\ln \left( {\frac{{{P_{bump}}}}{{{r_{bump}}}}} \right) } \right) \end{aligned}$$

(2d)

$$\begin{aligned} {C_{TSV1}}&= {C_{Underfill}} + {C_{IMD}} \end{aligned}$$

(2e)

$$\begin{aligned} {C_{TSV2}}&= {C_{Insulator}} + {C_{Bump1}} \end{aligned}$$

(2f)

$$\begin{aligned} {C_{TSV3}}&= {C_{Insulator}} + {C_{Bump2}} \end{aligned}$$

(2g)

$$\begin{aligned} {C_{TSV4}}&= {C_{Si sub}} \end{aligned}$$

(2h)

$$\begin{aligned} {C_{TSV5}}&= {C_{Underfill}} + {C_{Bottom}} \end{aligned}$$

(2i)

$$\begin{aligned} {G_{TSV}}&= {G_{Si sub}} \end{aligned}$$

(2j)

where $H_{TSV}$ and $H_{bump}$ are the height of TSV and bump, $P_{TSV}$ and $P_{bump}$ are the pitch between TSVs and between bumps.

Table 1 The parameters of the equivalent circuit in 2.5D PDN.

Table 1 describes the parameters of the equivalent circuit in the 2.5D PDN components. Upon completing the equivalent circuit modeling for each component, the cascade method is used to construct an overall system model, which generates the impedance matrix of the entire 2.5D PDN. This matrix serves as a key data source for power integrity analysis. In the subsequent electrothermal analysis, temperature fluctuations primarily influence the resistivity of the resistors. The resistance in the electrical model is defined as a temperature-dependent parameter, governed by the resistivity expression as (3).

$$\begin{aligned} \rho (T) = {\rho _0}(1 + {\alpha _0}(T - {T_0})) \end{aligned}$$

(3)

where T is the steady-state temperature of the 2.5D PDN, $T_0$ is room temperature, $\rho _0$ is the resistivity at room temperature (20 ${\circ }$C), and $\alpha _0$ is the temperature coefficient, which is specified according to the material properties of the actual model.

The parameters of the 2.5D PDN design are outlined in Table 2. These parameters are crucial for the accurate design, simulation, and fabrication of the 2.5D IC. This advanced 2.5D IC design demonstrates the integration of multiple chiplets with a carefully structured PDN, incorporating cutting-edge package techniques and high-k MIM capacitors to achieve superior performance.

Table 2 The model parameters and its values.

Thermal model

Fig. 3

Cooling structure of 2.5D (Si Interposer) chiplet package.

Fig. 3 illustrates an innovative and efficient heat dissipation solution for 2.5D ICs that utilizes TTSV technology to achieve efficient heat transfer and dispersion, significantly enhancing the system’s thermal management capabilities. It enables the direct and efficient transfer of substantial amounts of heat generated within the chiplets to the heat sink. Mitigating the risk of performance degradation or failure due to high chiplet surface temperatures ensures stable operation and prolongs the circuit’s service life. Furthermore, some of the Joule heat generated in the interposer can also be dissipated through this same pathway. By optimizing the location of the chiplets, local hot spots on the interposer can be avoided, further improving the overall heat dissipation efficiency of the 2.5D IC and enhancing both system performance and reliability.

To analyze the heat distribution with a 2.5D integrated system, the heat conduction equation based on Fourier’s law of heat conduction is typically employed. The heat conduction equation is a crucial partial differential equation that describes the heat transfer process, allowing for the analysis of heat propagating through space. Its general form is expressed as (4).

$$\begin{aligned} {\left\{ \begin{array}{ll} \rho c \frac{\partial T(x, y, z, t)}{\partial t} = \nabla (k(T) \nabla T(x, y, z, t)) + G(x, y, z)\\ T|_{\Gamma _a} = T_0\\ \frac{\partial T}{\partial n} |_{\Gamma _b} = -h(T - T_0) \end{array}\right. } \end{aligned}$$

(4)

where k(T) is the thermal conductivity of the material varying with temperature, c is the heat capacity of the material, $\rho$ is the density of the material, T(x, y, z, t) is the transient temperature distribution field function dependent on time and spatial coordinates, G is the internal heat generation source encompassing heat generated by the chiplet circuit modules and Joule heat in the interconnections, $\Gamma _a$ is the Dirichlet boundary, $T_0$ is the fixed temperature in the first type of boundary condition, typically set to room temperature (20 ${\circ }$C), $\Gamma _b$ is the Robin boundary, h is the convective heat transfer coefficient in the third type of boundary conditions, describing the heat transfer with the surrounding medium, and n is the normal vector indicating the direction of heat transfer which characterizes the directionality of the heat flow.

By solving the heat conduction equation with the specified boundary conditions, it becomes possible to predict the temperature distribution within the 2.5D IC system, thereby facilitating the design of effective thermal management strategies. In solid heat transfer problems, the equations can be solved using FVM. This method involves decomposing the computational region into multiple volume elements, establishing control equations for each element, and then integrating and solving these equations to derive the temperature distribution across the entire computational region. The 2.5D integrated system is divided into a series of repeating grid cells. These cells serve as discretized representations of space. For the steady-state heat transfer problem, the parameter of time is considered infinite, effectively eliminating the time-dependent term. When the thermal conductivity at the interface between two regions is discontinuous, the method of the harmonic mean can be employed to determine the equivalent thermal conductivity at the interface of the two finite volume elements. This approach ensures the continuity of heat flux across the interface.

Fig. 4

(a) Top view of the unit cell, (b) Different layers of unit cell.

In the process of solving the heat conduction equation for a 2.5D PDN using FVM, the thermal conductivity of the delineated grid volume cells must be determined in advance. Given the complex structure of grid-type PDNs and TSVs, a fine mesh delineation is essential to ensure accuracy in solving the heat conduction equation. To expedite the thermal analysis design, the equivalent thermal conductivity for the grid-type PDN and TSV structures will be deduced using coarser mesh volume cells in both vertical and horizontal directions, simplifying the mesh delineation when determining the temperature distribution of the 2.5D IC by FVM. Additionally, the heat removal capability of the interposer and chiplet PDN is considered in depth. Fig. 4 demonstrates the unique structure of the interposer and chiplet PDN unit cell, which comprises regularly spaced power and ground lines intertwined, with adjacent metal lines vertically connected through micro vias, separated by interlay dielectric (ILD). The metal interconnects within the PDN exhibit good thermal conductivity, promoting uniform heat distribution and significantly alleviating uneven temperature profiles inside the chiplets and interposer. This effectively reduces potential high-temperature hot spots and enhances the overall thermal stability of the chiplets. To simplify, it is assumed that chiplet PDN consists of two adjacent metal layers connected by a micro via layer, with dimensions corresponding to the chiplet size. The equivalent thermal conductivity of each segmented part is derived to facilitate the solution of FVM. The equivalent thermal conductivity of the PDN unit is derived as (5)²⁸.

$$\begin{aligned} {k_{xy\_{\textrm{PDN cell}}}}&= \frac{1}{3}({k_{x\_{\textrm{m}}}} + {k_{y\_{\textrm{m}}}} + {k_{xy\_{\textrm{v}}}}) \end{aligned}$$

(5a)

$$\begin{aligned} {k_{x\_{\textrm{m}}}}&= \frac{w}{p}{k_m} + \frac{{p - w}}{p}{k_{{\textrm{ILD}}}} \end{aligned}$$

(5b)

$$\begin{aligned} {k_{y\_{\textrm{m}}}}&= \frac{1}{{{w / {(p{k_m})}} + {{(p - w)} / {(p{k_{{\textrm{ILD}}}})}}}} \end{aligned}$$

(5c)

$$\begin{aligned} {k_{xy\_{\textrm{v}}}}&= {k_{{\textrm{ILD}}}}(\frac{{2p - {w_{\textrm{v}}}}}{{2p}}) + \frac{{2{w_{\textrm{v}}}}}{{{{(2p - {w_{\textrm{v}}})} / {{k_{{\textrm{ILD}}}} + {{{w_{\textrm{v}}}} / {{k_m}}}}}}} \end{aligned}$$

(5d)

$$\begin{aligned} {k_{z\_{\textrm{PDN cell}}}}&= \frac{3}{{2/{k_{z\_{\textrm{m}}}} + 1/{k_{z\_{\textrm{v}}}}}} \end{aligned}$$

(5e)

$$\begin{aligned} {k_{z\_{\textrm{m}}}}&= \frac{w}{p}{k_m} + \frac{{p - w}}{p}{k_{{\textrm{ILD}}}} \end{aligned}$$

(5f)

$$\begin{aligned} {k_{z\_{\textrm{v}}}}&= \frac{{w_{\textrm{v}}^2}}{{2{p^2}}}{k_m} + (1 - \frac{{w_{\textrm{v}}^2}}{{2{p^2}}}){k_{{\textrm{ILD}}}} \end{aligned}$$

(5g)

where w is the width of the grid metal, p is the pitch of adjacent metal lines, $w_v$ is the width of the micro via, $k_m$ and $k_{ILD}$ are the heat conductivity of metal and ILD, respectively.

Fig. 5

Top view of the TSV cell.

Fig. 5 illustrates the schematic structure of a TSV cell, which is composed of a copper TSV metal at its center, surrounded by a thin layer of silicon dioxide that serves as insulating material, and an outer silicon substrate. In the vertical direction, the copper acts as an excellent thermal conductor for heat transfer. However, in the horizontal direction, the insulating layer, despite its thinness, significantly impacts thermal resistance. The equivalent thermal conductivity of a TSV cell is derived as (6)²⁹.

$$\begin{aligned} {k_{xy,eq,TSV}}= 2\int _0^{{r_{TSV}} + {t_{OX}}} ({\frac{{dx}}{{{w_{xy,TSV,m}}(x)/{k_m} }}} +&\frac{{dx}}{{ {w_{xy,TSV,i}}(x)/{k_i} }} + {\frac{{dx}}{{ {w_{xy,TSV,s}}(x)/{k_s}}}}) \end{aligned}$$

(6a)

$$\begin{aligned} {k_{z,eq,TSV}}= \frac{{ {k_i}\pi [{{({r_{TSV}} + {t_{OX}})}^2} - {r_{TSV}}^2]+{{k_m}\pi {r_{TSV}}^2+{k_s}{{({r_{TSV}} + {t_{OX}})}^2}(4 - \pi )} }}{{4{{({r_{TSV}} + {t_{OX}})}^2}}} \end{aligned}$$

(6b)

$$\begin{aligned} {w_{xy,TSV,m}}(x)&= \sqrt{({r_{TSV}}^2 - {x^2})H({r_{TSV}}^2 - {x^2})} \end{aligned}$$

(6c)

$$\begin{aligned} {w_{xy,TSV,i}}(x)= \sqrt{{{({r_{TSV}} + {t_{OX}})}^2} - {x^2}} -\sqrt{({r_{TSV}}^2 - {x^2})H({r_{TSV}}^2 - {x^2})} \end{aligned}$$

(6d)

$$\begin{aligned} {w_{xy,TSV,s}}(x)&= {r_{TSV}} + {t_{OX}} - \sqrt{{{({r_{TSV}} + {t_{OX}})}^2} - {x^2}} \end{aligned}$$

(6e)

$$\begin{aligned} H(x)&= \left\{ {\begin{array}{*{20}{c}} {0,x \le 0}\\ {1,x > 0} \end{array}} \right. \end{aligned}$$

(6f)

where $r_{TSV}$ is the radius of the TSV metal, $h_{TSV}$ is the height of the TSV, $t_{OX}$ is the thickness of the oxide layer,  k_m is the thermal conductivity of the metal,  $k_i$ is the thermal conductivity of the insulating layer, and $k_s$ is the thermal conductivity of the substrate.

Fig. 6

The illustration of the TSV array.

Fig. 6 depicts the TSV array where the TSVs are uniformly distributed throughout the substrate. The equivalent thermal conductivity of the TSV array is derived as (7).

$$\begin{aligned} {k_{x,eq,TSVarray}}= \frac{{{k_{x,eq,TSV}}(w - N{w_{TSV}})}}{w} \nonumber + \frac{{{k_s}Nl{w_{TSV}}}}{{(l - M{l_{TSV}})w}}//\frac{{{k_{x,eq,TSV}}Nl{w_{TSV}}}}{{M{l_{TSV}}w}} \end{aligned}$$

(7a)

$$\begin{aligned} {k_{y,eq,TSVarray}}= \frac{{{k_{y,eq,TSV}}(l - M{w_{TSV}})}}{l} +\frac{{{k_s}M{l_{TSV}}w}}{{l(w - N{w_{TSV}})}}//\frac{{{k_{y,eq,TSV}}M{l_{TSV}}w}}{{Nl{w_{TSV}}}} \end{aligned}$$

(7b)

$$\begin{aligned} {k_{z,eq,TSVarray}}= \frac{{{k_{z,eq,TSV}}MN{l_{TSV}}{w_{TSV}} }}{{lw}}+\frac{{ {k_s}(lw - MN{l_{TSV}}{w_{TSV}})}}{{lw}} \end{aligned}$$

(7c)

$$\begin{aligned} {w_{TSV}}&= {l_{TSV}} = 2({r_{TSV}} + {t_{ox}}) \end{aligned}$$

(7d)

$$\begin{aligned} a//b&= \frac{{ab}}{{a + b}} \end{aligned}$$

(7e)

where w and l are the width and length of the substrate. $w_{TSV}$ and $l_{TSV}$ are the width and length of a TSV unit. The equivalent thermal conductivity of the bonding layer with bumps can be similarly derived as the TSV array.

Optimization method based on the HMO algorithm

The incorporation of TTSVs into chiplets in 2.5D ICs enables efficient heat transfer to the heat sink, thereby significantly improving thermal management. However, the fabrication of TTSVs introduces additional manufacturing cost to the chiplets. To balance electrothermal performance and manufacturing cost, an intelligent optimization method is proposed to optimize the design parameters of TTSVs and the placement of chiplets. Based on the desired electrothermal performance of a 2.5D IC with TTSV cooling, the multiobjective optimization criteria are established. Then the design parameters of TTSVs and the placement of chiplets are optimized by the proposed optimization algorithm. Finally, the design parameters are obtained using the proposed method. The accuracy of the proposed method is validated through finite element method (FEM) simulations.

Multi-objective optimization criterion for 2.5D PDN with TTSV cooling

The optimization process involves formulating multi-objective criteria that balance various performance factors. In terms of thermal management, it focuses on ensuring efficient heat dissipation and avoiding hotspots to maintain the operational stability and longevity of the 2.5D IC. In terms of electrical performance, the goal is to minimize impedance effects to optimize power integrity. In terms of manufacturing cost, the aim is to reduce the overall fabrication costs associated with signal wires and TTSV implementation. It requires determining the size and spacing of TTSVs to enhance thermal conductivity while minimizing manufacturing expenses. Additionally, the positioning of chiplets on the interposer must be optimized to achieve shorter overall wire lengths, uniform heat distribution, and optimal electrical performance. The expression for the multi-objective optimization criterion considering electrical and thermal characteristics along with manufacturing cost is given by (8).

$$\begin{aligned} \Psi&= {\lambda _1}{\psi _1} + {\lambda _2}{\psi _2} + {\lambda _3}{\psi _3} \end{aligned}$$

(8a)

$$\begin{aligned} {\psi _1}= \frac{1}{4}\sum \limits _{i = 1}^4 {\sum \limits _{f \in \Gamma } {( {Z_{chiplet,i}}} } + {\alpha _1}\max (0,{Z_{chiplet,i}} - {Z_{target}})) \end{aligned}$$

(8b)

$$\begin{aligned} {\psi _2}&= \frac{1}{4}\sum \limits _{i = 1}^4 {({T_{chiplet,i}}} + {\alpha _2}\max (0,{T_{chiplet,i}} - {T_{\max }})) \end{aligned}$$

(8c)

$$\begin{aligned} {\psi _3}&= {\textrm{cos}}{{\textrm{t}}_{TTSV}} + {\textrm{cos}}{{\textrm{t}}_{wire}} \end{aligned}$$

(8d)

where $\psi _1$ is the summation of the actual chiplet impedance, $\psi _2$ is the temperature of chiplets, $\psi _3$ is the manufacturing cost associated with the TTSVs and signal wires, $\alpha$ is the penalty coefficient, and $\lambda$ is the weighting factor which can be customized and modified in real-time based on performance priorities. For instance, when thermal management and electrical performance are deemed equally critical and both twice as important as manufacturing cost, the weighting coefficients can be correspondingly assigned as $\lambda _{1} = 0.4$, $\lambda _{2} = 0.4$, and $\lambda _{3} = 0.2$, ensuring the normalization condition ($\sum \limits _{i=1}^3{\lambda _{i}} = 1$) is satisfied. This weighting scheme allows for the prioritization of competing objectives in multi-objective optimization scenarios.

Optimization method based on the HMO algorithm

The intelligent optimization design method is developed using a hybrid metaheuristic optimization (HMO) algorithm. The main loop of the algorithm employs a modified particle swarm optimization (PSO) algorithm with a linearly decreasing inertia weight (LDIW). The update equation for PSO algorithm is denoted as (9).

$$\begin{aligned} V_i^{k}= \omega (k)V_i^{k-1} + {c_1}{r_1}(p_i^{k-1} - x_i^{k-1})+ {c_2}{r_2}(g^{k-1} - x_i^{k-1}) \end{aligned}$$

(9a)

$$\begin{aligned} X_i^{k }&= V_i^{k } + X_i^{k-1} \end{aligned}$$

(9b)

where $i=1,2,..., R, k=1,2,..., K,$ R is the total number of particles, K is the maximum number of iterations, $V_i^k$ denotes the velocity of the i-th particle in the k-th generation, $X_i^k$ denotes its position, $p_i^k$ denotes the locally optimal solution of the i-th particle in the k-th generation, $g_k$ denotes the globally optimal solution in the same generation, $c_1$ and $c_2$ are the local and global learning factors, respectively, which influence how particles approach the previous generation’s locally and globally optimal solution, $r_1$ and $r_2$ are uniform random numbers in the range of [0,1], and $\omega$ is the inertia weight factor. In the traditional PSO algorithm, $\omega$ is typically constant. When employing higher $\omega$ values, particles exhibit greater momentum preservation, which promotes exploratory behavior by enabling broader search space coverage. While this approach leads to slower convergence rates, it effectively mitigates the risk of premature convergence to local optima. Conversely, lower $\omega$ values cause particles to rapidly dissipate their inertia, concentrating the search around current best solutions. Although this strategy accelerates convergence speed, it simultaneously increases susceptibility to local optima entrapment. To achieve an optimal balance, dynamic inertia weight strategies have been developed. A representative approach is the PSO-LDIW method, where $\omega$ is systematically reduced according to iteration progress. Its expression is given by (10).

$$\begin{aligned} \omega (k) = {\omega _{start}} - ({\omega _{start}} - {\omega _{end}})\left( {\frac{{K - k}}{K}} \right) \end{aligned}$$

(10)

where $\omega _{start}$ and $\omega _{end}$ are the inertia weight factors at the beginning and end of the algorithm, respectively. By utilizing linearly decreasing inertia weights, the PSO-LDIW algorithm exhibits strong global search capabilities during the initial stages of the search, enabling it to quickly locate an approximate position within the solution space. As the iteration progresses, the inertia weights gradually decrease, allowing the algorithm to shift towards a local search that finely tunes the quality of the solution. This adaptive adjustment of the search strategy throughout the optimization process generally results in faster convergence speeds. By carefully introducing inertia weights and optimizing parameter settings, the PSO-LDIW algorithm can effectively mitigate the risk of becoming trapped in local optima.

In the particle boundary condition processing, the Metropolis criterion from the simulated annealing algorithm is employed to enhance the diversity of the particles within the algorithm. If the new generation of particles fails to meet the boundary conditions, a sub-optimal position of a particle is selected to replace the global optimal position, allowing for the update of the new particle. It facilitates a characteristic of probability jumps. Its expression is given by (11).

$$\begin{aligned} {P_i}&= {e^{ - \frac{{f({p_i}) - f(g)}}{T}}}/\sum \limits _{i = 1}^R {{e^{ - \frac{{f({p_i}) - f(g)}}{T}}}} \end{aligned}$$

(11a)

$$\begin{aligned} P_j^{sum}&= \sum \limits _{i = 1}^j {{P_i}} \end{aligned}$$

(11b)

$$\begin{aligned}&\begin{array}{l} if\, P_j^{sum} \ge {r_3}\\ {g^k} = p_j^k\\ end \end{array} \end{aligned}$$

(11c)

where $P_i$ is the probability of a particle under the Metropolis criterion, $P_j^{sum}$ is the cumulative probability of selecting a new particle, and $r_3$ is a uniform random number in the range of [0,1].

To further enhance the diversity of the population, differential evolution is applied to perform mutation and crossover operations on the particles, facilitating the hybrid metaheuristic optimization algorithm’s ability to more effectively locate the global optimal solution. Its expression is given by (12).

$$\begin{aligned} q_i^k&= p_i^k + \theta (p_{i'}^k - p_{i''}^k) \end{aligned}$$

(12a)

$$\begin{aligned} q_{i,d}^k&= \left\{ {\begin{array}{*{20}{c}} {p_{i,d}^k,{r_4} \ge \theta }\\ {q_{i,d}^k,{r_4} < \theta } \end{array}} \right. \end{aligned}$$

(12b)

where $q_i^k$ is the k-th generation mutated particle, $p_i^k$ is the k-th generation locally optimal particle, $p_{i'}^k$ and $p_{i''}^k$ are two distinct particles different from $p_i^k$, $p_{i,d}^k$ denotes the d-th dimensional element of $p_i^k$, $\theta$ is the mutation operator, and $r_4$ is a uniform random number in the range of [0,1].

Fig. 7

Flowchart of the proposed intelligent design method.

The specific flow framework of the electrothermal co-optimization algorithm is illustrated in Fig. 7. The process begins with the establishment of the electrical and thermal models for the 2.5D PDN to predict impedance and temperature distributions. Next, based on the desired electrothermal performance of the 2.5D PDN with TTSV heat dissipation, a multi-objective optimization criterion related to electrothermal performance and manufacturing cost is formulated. The proposed hybrid metaheuristic optimization algorithm then optimizes the design parameters of TTSVs and the distribution of chiplet locations. The detail of the HMO algorithm is presented in Algorithm 1. In the final step, the optimal design parameters are obtained and the accuracy of the results is verified.

Algorithm 1

HMO algorithm for the electrothermal co-optimization of 2.5D PDN.

Verification and Discussion

Table 3 The materials of the model case.

To comprehensively verify the effectiveness and efficiency of the proposed method, a model case is constructed as shown in Fig. 1. Table 3 lists the materials of the modeling case. The thermal parameters of materials are derived³⁰. The MIM capaciotr is set to 50fF in each cell with the decap. Note that in our previous work³¹, the package was modeled with high thermal flux applied in all directions, rather than adiabatic boundaries, resulting in relatively low operating temperatures with higher power density. In this case, the system is re-modeled using adiabatic boundaries, allowing heat conduction only through the heat sink on the top of package. It leads to higher temperatures with lower power density, better reflecting real-world conditions.The model is optimized for a multi-chiplets scenario, where the thermal power density of each chiplet is set to different values to simulate complex thermal distribution scenarios encountered in real applications. The thermal power densities of the four chiplets are assumed to be 185 W/cm², 170 W/cm², 215 W/cm², and 200 W/cm², respectively, with a maximum allowable operating temperature of 80 ${\circ }$C. Manhattan wiring rules are applied to connect the signal lines between the chiplets. Another key optimization design parameter is the spacing range of TTSV, set between 30 $\mu$m and 70 $\mu$m. In the conventional design, using a uniformly distributed TTSV layout strategy, the range of the fitness value is calculated to be [763.1, 1504.6] based on the proposed optimization criterion ($\Psi$). There is a substantial optimization space for the conventional scheme. The object of implementing the optimization algorithm is to adjust the design parameters through several iterations to minimize the fitness value, achieving a balance between chiplet impedance, heat dissipation efficiency, and manufacturing cost. The computer hardware for the proposed calculation and Subsequent simulation verification mainly includes an Intel(R) Xeon(R) Gold5217 CPU, 64 GB RAM, 3 GHz working frequency.

Fig. 8

Iteration of different algorithms.

Table 4 The parameters and value of optimization algorithms.

Table 5 Comparison of the different algorithms.

Fig. 8 compares the iteration process of different metaheuristic optimization algorithms with the same number of function evaluations. The key parameters of the optimization algorithms are listed in Table 4. After multiple iterations, the fitness value stabilizes at a lower level, indicating that the algorithm has successfully identified the optimal or near-optimal design solution under the current constraints. The iteration results demonstrate that a single optimization algorithm may prematurely converge to a locally optimal solution or sub-optimal solution, whereas the proposed hybrid metaheuristic optimization algorithm can discover a more optimal solution. Table 5 compares the time complexity, the specific runtime, and final fitness values of various metaheuristic optimization algorithms, including PSO²², SA²³, and DE³² as well as their hybrid variants, where O denotes the complexity of the algorithm and D represents the dimension of each particle. In addition, to evaluate the performance differences between the algorithms, each algorithm is independently executed 20 times to optimize the objective function. A Wilcoxon signed-rank test is then conducted on the optimal fitness values obtained from the proposed algorithm and the comparative algorithms. The resulting p-values are all statistically significant (p<0.05), demonstrating that the proposed algorithm exhibits significantly different performance characteristics compared to the other algorithms. The proposed hybrid metaheuristic optimization algorithm achieves the smallest final fitness value, approaching the optimal solution despite the increased time complexity.

Fig. 9

Optimized location of Chiplets (Red lines represent the signal wiring region between chiplets).

By implementing the proposed electrothermal co-optimization method, the optimization results are illustrated in Fig. 9, showcasing the overall distribution of the chiplets and the signal wiring within the optimized 2.5D system structure. The scheme achieves a balance between the PDN’s electrothermal characteristics and manufacturing cost, effectively preventing localized hot spots in the interposer caused by closely placed chiplets, while also avoiding excessive signal wire lengths due to overly dispersed chiplets. Additionally, it meets the design requirements for the target impedance of chiplets. The spacing parameters of the TTSVs are presented in Table 6, indicating that the TTSVs in chiplets with higher power densities are spaced closer together. The denser distribution of TTSVs enhances the vertical heat dissipation of the chiplets.

Table 6 Pitch of TTSVs in different chiplets.

Fig. 10

Comparison of chiplet impedance curves.

Fig. 11

Temperatures of (a) the proposed method and (b) FEM.

To further quantify the results, Fig. 10 compares the impedance curves of different chiplets. The results demonstrate that the impedance values of all four chiplets meet the target impedance; Additionally, Fig. 11 compares the temperature distributions obtained using the proposed method with those derived from FEM. The comparison shows that the chiplet temperatures satisfy the maximum temperature constraints (< 80 ${\circ }$C), confirming the efficiency of TTSVs in transferring the heat to the heat sinks. The impedance values and average temperatures of the different chiplets in the optimized 2.5D system structure are listed in Table 7 and Table 8, respectively. These values are verified and compared against the FEM simulation results with the Mean Absolute Error (MAE) of 3.97$\%$ and $0.35\%$, respectively. The small error is mainly due to the computational approximation of the equivalent model. The accuracy of impedance and temperature distributions in the optimized 2.5D PDN structure proves that the proposed method is highly accurate and provides an effective model for the optimal electrothermal design of 2.5D integration systems.

Table 7 Impedance of different methods.

Table 8 Temperatures of different methods.

Conclusion

An electrothermal co-optimization method for a 2.5D PDN with TTSV cooling is proposed. The hybrid metaheuristic optimization algorithm achieves superior performance (fitness value = 310.3) in optimizing TTSV distribution and chiplet placement. Validation demonstrates excellent agreement with finite element simulations, showing merely 3.97$\%$ and 0.35$\%$ average absolute errors in impedance and temperature predictions, respectively. The proposed method offers an effective solution for high-performance 2.5D microsystems, balancing thermal management, power integrity, and manufacturing cost.

Several research directions remain for future work: (1) Conducting a comprehensive sensitivity analysis of the parameters in the optimization algorithm. (2) Incorporating machine learning techniques to enhance algorithmic performance. (3) Extending the model to encompass a full 3D IC. (4) Employing multiple optimization algorithms and experimental measurements for comparative validation.