A backplane circuit including a thin-film transistor (TFT) array is essential for active driving of organic light-emitting diode (OLED) displays. As an active semiconductor for such a TFT, an oxide semiconductor material such as amorphous indium-gallium-zinc-oxide (a-IGZO) or polysilicon is mainly applied. Particularly, in the case of large-area active-matrix OLED (AMOLED) displays, a-IGZO semiconductor suitable for large-area uniform deposition is growing in importance as a key semiconductor material for the backplane. A conventional fabrication process of a TFT consists of sequential vacuum deposition, photolithography, and plasma etching processes of various thin films constituting the TFT. Since these series of processes are carried out in a bottom-up manner, starting from the substrate and stacking up one layer at a time, there have been disadvantages of requiring a large number of processes as well as difficulty in maintaining overlay accuracy. Among these TFT manufacturing processes, especially in the photolithography process, as a method for eliminating the difficulty of repetitive pattern alignment and dramatically reducing the number of processes, a self-aligned imprint lithography (SAIL) process has been proposed and studied1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16. Unlike the conventional TFT fabrication process, this SAIL process is a top-down method of realizing TFT by depositing all the thin films constituting the TFT on the substrate in advance and removing unnecessary parts by plasma etching. 3–5,15,16 Here, as an etch mask for defining unnecessary parts, a polymer resin having a three-dimensional (3D) structure obtained through an imprint process is used. Since the imprinted 3D resin structure serves as a multi-layer stacked etch mask that is already aligned, there is no concern about overlay accuracy problems. Moreover, it has the advantage of being simple and fast as the entire process consists of only one imprint and sequential plasma etching process16.

The previous study focused on validating the conceptual feasibility of the SAIL process at the single-device level. 1–16 In contrast, this paper quantitatively verifies the electrical uniformity and process reproducibility of a complete 5 × 5 TFT array. The SAIL process was extended to a functional array scale with optimized pattern design, and statistical analysis of 25 individual devices experimentally confirmed that stable operation was achieved without misalignment or non-uniformity. In addition, optimization of the etching process improved pattern uniformity, and adjustment of the IGZO active layer and dielectric thickness resulted in improved subthreshold swing (SS). Therefore, this study does not merely reproduce the previous SAIL process but advances it in terms of device integration, process precision, and electrical uniformity.

In this study, we report on the fabrication process and characterization results of 5 × 5 a-IGZO TFT array utilizing the SAIL process4,6,14,15,16. First, a five-story, pre-aligned 3D master template was realized on a silicon (Si) wafer, integrating all structural information from five distinct reticle patterns. An imprint stamp with an identical structure was then fabricated on a plastic substrate by molding the master template with an ultraviolet (UV)-curable resin. Concurrently, a multilayer stacked thin-film sample, comprising all a-IGZO TFT array layers, was fabricated on a separate glass substrate with a polymer resin layer coated on its surface. The resin layer was then imprinted with the pre-prepared stamp to form a 3D etch mask. By sequentially plasma etching the five stories of the etch mask one by one, the exposed surfaces of the underlying thin films were also sequentially etched, culminating in the fabrication of the final a-IGZO TFT array. To mitigate short-circuiting between gate and data lines and to eliminate parasitic capacitance in the TFT array, undercut holes were introduced in multiple locations.3–6,14−16 This study experimentally demonstrates that the developed SAIL process enables the fabrication of a-IGZO TFT arrays through a single imprinting step followed by a series of continuous plasma etching processes, entirely obviating the need for conventional photolithography. All 25 fabricated TFTs exhibited stable switching characteristics, with high uniformity in mobility, on/off ratio, and threshold voltage being experimentally confirmed.

Results and discussion

Fabrication of master template and imprint stamp

The master template used to produce the imprint stamp was fabricated as a 3D structure on a Si wafer by repeatedly applying photolithography and plasma-etching processes using 5 different reticles. This template encompasses the structure of a 5 × 5 a-IGZO TFT array and pad electrodes for the operation of these transistors. Figure 1 shows the fabrication sequence of the master template for a unit TFT structure within a 5 × 5 TFT array. The figure shows side views and cross-sectional depths, with areas of different depths indicated by arrows. First, the area excluding the TFT and electrode lines was etched to a depth of 10 μm [Fig. 1(a)], and then the gate line area was etched to a depth of 2 μm to form the structure shown in Fig. 1(b). The channel area of the transistor was then additionally etched to have a step of 1.8 μm [Fig. 1(c)]. Finally, the entire Si substrate was additionally etched to a depth of 1.8 μm, and then the undercut holes, as indicated by circles in Fig. 1(d), were etched to a depth of 8.2 μm to complete the master template. The depth of the pattern with the lowest depth and the depth of the undercut holes were made the same. These undercut holes were installed at two locations (3 holes each) on each source line and at two locations (2 holes each) on the left and right sides of the channel, with the size of each hole being 15 × 20 µm2. The final TFT shown in Fig. 1(d) has a 5-story structure, with each floor having a different height. In addition, the drain electrode was designed considering the OLED driving structure, where OLED pixels are directly stacked on top of the TFT array. This design provides a foundation for extending the same SAIL process to future OLED pixel-driving circuits.

Fig. 1
figure 1

Schematic diagram showing the fabrication process of a master template having transistor and wiring-electrode patterns in a 5-story structure.

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To produce an imprint stamp, an UV-curable resin was uniformly applied onto a completed master template, a polyethylene terephthalate (PET) film to be used as a stamp substrate was attached, and UV curing was performed simultaneously while applying pressure with a roller to produce a stamp. The pattern transfer from the master template to the imprint stamp is illustrated in Fig. 2(a). Simultaneously with the molding of the stamp, all material layers constituting the a-IGZO TFT were sequentially deposited on a separate glass target substrate and finally coated with polyurethane (PU) resin to prepare a sample as shown in Fig. 2(b). The gate electrode, gate dielectric, IGZO semiconductor, and source/drain (S/D) electrodes were deposited in order on the entire surface of the glass substrate, and the materials and thicknesses of each layer used are shown in Fig. 2. Among the various resins tested in advance, a resin with high viscosity and fast UV curing, which enables the 3D pattern of the stamp to be precisely imprinted, was selected and used. In order to facilitate the demolding after the pattern transfer using the stamp, the surface of the stamp was surface-treated with an octadecyltrichlorosilane (ODTS) self-assembled monolayer (SAM). Figures 2(b), 2(c), and 2(d) schematically illustrate the imprint and demolding processes. It was experimentally confirmed that the finally imprinted TFT array patterns were transferred almost identically to the master template.

Fig. 2
figure 2

Schematic diagram showing the process from the step of making an imprint stamp from a master template to the transfer of the pattern onto the resin surface of the sample.

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Fabrication of a 5 × 5 a-IGZO TFT array using SAIL process

The optical microscope image and structural diagram of the TFT array pattern imprinted on the PU resin on the sample surface are shown in Fig. 3(a). Because the overall structure of the TFT array is complex, the structural diagrams in Fig. 3 only show a single TFT within the array. The pattern of the single TFT in the optical microscope image [Fig. 3(a)] was transferred identically to that of the master template shown in Fig. 1(d). First, the thinnest area of the resin pattern, i.e., the area excluding the TFT and electrode lines, was plasma etched to expose the S/D aluminum (Al) electrode layer [Fig. 3(b)]. After etching the exposed S/D Al layer, the Cr, IGZO, gate dielectric (SiNx, SiO2), and gate Al layers underneath were successively plasma-etched to expose the glass substrate [Fig. 3(c)]. Since the Al gate electrode on the bottom surface is connected to both the gate line and the source line, it is necessary to separate the lines. As shown in Fig. 1(d), since the undercut holes have the first floor height in the resin pattern, all layers beneath the undercut holes are etched equally during the etching process of Figs. 3(b) and 3(d). Overetching of the bottom gate Al layer is necessary to ensure complete disconnection of the gate line and source line. The dotted circles in Fig. 3(d) indicate that the source lines are disconnected by undercut etching through the holes. Since the resin thickness of the gate line is thinner than that of the source line or the S/D channel, when the resin is etched to a certain thickness, the Al surface of the gate line is exposed first, as shown in Fig. 3(e). The photographic image of Fig. 3(e) shows that only the gate lines are exposed. The structure in Fig. 3(f) was obtained by etching Al, Cr, and IGZO sequentially. The reason for leaving the gate line dielectric layer was to protect the gate line Al electrode from being directly exposed to plasma during the etching of the resin in the TFT channel region and the Al layer above the channel. The residual gate line dielectric layer therefore served to minimize plasma damage to the gate electrode during the plasma etching of the channel region. Finally, the Cr layer in the channel area was sequentially removed to expose the IGZO layer, resulting in the final structure shown in [Fig. 3(g)]. By comparing the optical microscope images before and after etching, it was particularly observed at the initial stage [Fig. 3(b)] whether the polymer resin was etched uniformly. Furthermore, analysis of the final patterned images confirmed that uniform etching was achieved across all regions, thereby demonstrating that the etching uniformity was successfully maintained throughout the process. Since the IGZO channel layer may be damaged during the plasma etching process, the Cr layer in the channel area in particular was removed by wet etching. The reason for using the Cr layer is that Cr has a very slow etching rate by plasma and commercial wet etchants that can easily remove Cr are available. Figure 3(h) shows the structure of a single TFT, which was finally completed after removing the remaining resin. As described so far, since the 3D resin pattern contains all the information of the etch masks required for the TFT, an a-IGZO TFT array can be easily fabricated with only a single imprint process and successive plasma etching processes.

Fig. 3
figure 3

Fabrication sequence of IGZO TFT array by sequential plasma etching and optical microscope images corresponding to each sequence.

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The plan and side view images of the final single transistor are shown in Fig. 4(a). In order to clearly understand the structure of the fabricated transistor, each layer is shown separately in Fig. 4(b). The top S/D Al/Cr layer has separated source and drain, and the IGZO and dielectric layers below it have the same structure with connected channels. The bottom gate Al layer has a structure in which the left and right of the channel and the top and bottom of the data lines are separated and isolated from the gate lines. This separation of the data lines was achieved by undercut etching of the bottom Al electrode using the undercut holes prepared in the data lines as passages for the etching gas, as described above. Since the glass substrate is transparent, it is possible to confirm from below with an optical microscope whether the left and right of the channel and the top and bottom of the data lines are disconnected as expected at the bottom Al electrode. As can be confirmed from the reflection images of the structures within the dotted lines in Figs. 4(c) and 4(d), it was confirmed that the left and right of the channel and the top and bottom of the data lines were completely disconnected by undercut etching. The disconnection of the bottom gate Al layer on the left and right sides of the channel is particularly important to reduce the parasitic capacitance of the TFT array. Figure 4(e) shows an enlarged top-view image of the selected region, indicating that the upper source/drain electrodes were not affected by the undercut etching process. Figure 4(f) shows the SEM image of the region area f in Fig. 4(e). To more clearly verify whether the bottom Al layer was undercut etching, the g area in Fig. 4(f) was cut using FIB, and the resulting cross-sectional structure is presented in Fig. 4(g). In general, when the bottom region has been removed by undercut etching, the upper film tends to lift upward during FIB cutting, causing it to appear thicker than its actual thickness. As shown in Fig. 4(g), the bottom Al layer around the hole was completely removed by the undercut etching process.

Fig. 4
figure 4

(a) Plan view and side view images of the fabricated single TFT, (b) exploded view of each layer of the single TFT, (c) optical microscope image of the fabricated TFT array taken under the glass substrate, (d) enlarged images thereof, (e) enlarged top view images thereof, (f) SEM image near the channel, (g) cross-sectional SEM image near hole cut with FIB.

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The completed 5 × 5 a-IGZO TFT array was designed with a channel width and length of 50 μm, and transfer curves were measured to analyze the electrical characteristics of the TFTs. The measurements were performed by varying the gate voltage from − 35 V to + 40 V, with ground applied to the source electrode and 0.5 V to the drain electrode. To distinguish each transistor device, the gate line pads and data line pads were assigned numbers 1 to 5 and letters A to E, respectively. [Fig. 5(a)] For example, device number 1 A indicates a device connected to gate line 1 and data line A. The current-voltage (I-V) curves were measured while sequentially changing the data lines while fixing the gate line, and the results are shown in Figs. 5(b) to 5(f). Figure 5(g) shows the output characteristic curves of a representative TFT selected from the 5 × 5 TFT array, measured by varying the drain voltage from 0 V to 30 V and the gate voltage from 0 V to 30 V in 5 V increments. The measured results showed that the average linear mobility was 13.8 cm2/V·s and the standard deviation was 1.53 cm2/V·s under a gate voltage of 20 V. [Fig. 5(h)]The on/off current ratio was 3.92 × 106 on average, and the standard deviation on the log-scale was 0.52. [Fig. 5(i)] The average threshold voltage (Vt) was − 8.58 V and the standard deviation was 0.62 V. Consistent I–V characteristics were observed in all TFTs, and the on/off ratio and Vt showed high uniformity across the TFTs. [Fig. 5(j)] At low drain voltages (Vd), the drain current increased linearly, clearly defining the linear region, while with increasing Vd, the channel gradually became pinched off and the drain current transitioned to the saturation region, exhibiting the typical behavior of an n-type TFT.

For comparison, TFT samples with the same channel dimension (50 × 50 μm) were fabricated using a conventional bottom-up photolithography process. The schematic and optical microscope images of the fabricated samples are shown in Fig. 6(a) and Fig. 6(b), respectively, and their I–V characteristics compared with those of the SAIL-fabricated devices are shown in Fig. 6(c). The devices fabricated using the photolithography process exhibited a linear mobility of 12.2 cm²/V·s, a threshold voltage of − 8.18 V, and an on/off current ratio of 5.56 × 106. These results showed no significant difference from those of the SAIL-fabricated devices, further confirming that imprint lithography can simplify the fabrication process while achieving device characteristics comparable to those obtained by the conventional method. This result well reflects the excellent reproducibility and precision of the device fabrication process, supporting the possibility of applying the SAIL process to large-area TFT arrays. An issue that needs to be addressed in the experimental results obtained in this study is that the Vt of all TFTs have negative values. These results are attributed to the diffusion of hydrogen contained in the PECVD-deposited SiNx gate dielectric into the IGZO active layer during 400 °C annealing process. 17,18,19,20,21,22 As shown in Figs. 7(a) and 7(b), elastic recoil detection (ERD) analysis revealed that the SiNx film deposited at 80 °C by PECVD contained a high hydrogen concentration of 26.38 at%, whereas the SiO2 film deposited at 250 °C exhibited only 6.3 at% hydrogen. Because hydrogen has an extremely small atomic radius and a high diffusion coefficient, it readily diffuses into neighboring layers under thermal processing conditions. Figure 7(c) shows the electrical characteristics of the device using SiNx as the gate insulator, while Fig. 7(d) corresponds to the device using only SiO2. The SiNx-based TFT exhibited a significant negative shift in the Vt, whereas the TFT with only SiO2 did not show such a negative shift. This behavior is attributed to excessive hydrogen originating from the SiNx layer diffusing into the IGZO and acting as a shallow donor. Therefore, controlling the hydrogen concentration within the SiNₓ layer is crucial for controlling Vt and ensuring the reliability of IGZO TFTs.

Fig. 5
figure 5

(a) Optical microscope images of the a-IGZO TFT array; (b)–(f) Transfer curves of 5 TFTs in the same row of the TFT array; (g) representative output characteristics (h) linear mobility, (i) on/off ratio, and (j) threshold voltages of all 25 TFTs in the TFT array.

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Fig. 6
figure 6

(a) Schematic diagram of a TFT fabricated with a conventional process using photolithography; (b) Optical microscope image of the TFT with a channel dimension of 50 × 50 μm; (c) Transfer curves of TFTs fabricated by the SAIL and photolithography processes.

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Fig. 7
figure 7

ERD analysis of PECVD-deposited (a) SiNx at 80 °C and (b) SiO2 at 250 °C; Transfer characteristics of (c) TFT with SiNx gate insulator and (d) TFT with SiO2 gate insulator.

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Conclusions

It was experimentally demonstrated that a 5 × 5 a-IGZO TFT array could be fabricated using the SAIL process without the use of photolithography. Since all patterns within this TFT array were already self-aligned to the 3D etch mask obtained by the imprint process, uniform devices could be obtained without problems such as pattern misalignment or overlapping. By forming undercut holes in this 3D etch mask and undercut-etching the bottom electrode through them, it was shown that the gate and source lines constituting the TFT array could be disconnected and the parasitic capacitance around the gate electrode could be reduced. The linear mobility and Vt of all 25 fabricated TFTs were 13.8 ± 1.53 cm2/V‧s and − 8.58 ± 0.62 V, respectively, showing nearly uniform switching characteristics. The negative Vt shift of all devices is believed to be due to hydrogen diffusion from the low-temperature deposited SiNx gate dielectric into the IGZO active layer. Therefore, a hydrogen barrier capable of preventing hydrogen diffusion is expected to be required in future work. In addition, comparison with reference devices fabricated by a conventional photolithography process confirmed that the SAIL approach provides comparable electrical performance while offering significant process simplification. This study experimentally demonstrated that a 5 × 5 a-IGZO TFT array can be realized using a simplified process that excludes photolithography, and it can serve as a key foundational technology for future applications such as flexible large-area display backplanes.

Methods

The TFT substrate glass was first ultrasonically cleaned with acetone and methanol for 10 min each. The Al gate electrode was deposited to a thickness of 150 nm by magnetron sputtering, followed by sequential deposition of SiO2 (150 nm) and SiNx (100 nm) as gate dielectrics at 250 °C and 80 °C, respectively, by plasma-enhanced chemical vapor deposition (PECVD). The gate dielectric was designed as a bilayer structure to ensure stable interfacial quality between the Al gate electrode and the IGZO semiconductor layer. The bottom SiO2 layer provides excellent insulating properties and a low interface defect density, thereby improving the dielectric stability at the Al gate interface. In contrast, the upper SiNx layer, which has a relatively higher dielectric constant, enhances the charge induction efficiency, allowing more effective carrier accumulation in the IGZO channel and consequently improving the effective mobility of the device. 23,24,25, As the active layer, a-IGZO was deposited to a thickness of 30 nm by magnetron sputtering using a target with a molar ratio of In2O3:Ga2O3:ZnO of 1:1:1. After IGZO deposition, annealing was performed at 400 °C for 1 h to improve semiconductor properties. Al is one of the metals prone to hillock formation under thermal stress and grain growth during the annealing process. Such hillock formation can increase the surface roughness of the gate electrode and result in higher electrical resistance. The samples used in this study consisted of a multilayer structure of Al/SiO2/SiNx/IGZO on a glass substrate, where the gradual variation in thermal expansion coefficients among layers effectively alleviated thermal stress accumulation in the Al layer. 26,27 Consequently, excessive compressive stress that could induce hillock formation was not generated. As shown in Figs. 5(b) to 5(f), all TFTs exhibited uniform transfer characteristics when gate voltage was applied, supporting that no hillock formation occurred during the annealing process. Finally, a Cr (15 nm)/Al (100 nm) layer to be used as the S/D electrode was deposited to complete the sample fabrication.

The PU resin with a 3D structure formed on the surface of the sample was used as an etch mask to remove several underlying material layers by reactive ion etching (RIE). Sputter etching using Ar/O2 (30/10 sccm, 400 W) was performed to open the thinnest region in the 3D resin structure. After this process, the exposed S/D Al layer was etched using a Cl2/BCl3 mixed gas (5/20 sccm, 60 W), and the Cr layer was plasma-etched using Cl2 (30 sccm, 120 W) gas. Subsequently, the IGZO layer was sequentially etched using BCl3 (25 sccm, 180 W) gas, and the gate insulating layers, SiNx and SiO2, were sequentially etched with CF4 (30 sccm/80 W for SiNx and 20 sccm/70 W for SiO2) gas. Finally, when removing Cr in the channel region, wet etching was performed using a wet Cr etching solution (ETCR-400) diluted to 10% to prevent plasma damage to IGZO. The etching process conditions are summarized in Table 1. A more specific etching process sequence is described in detail in the results and discussion section of this paper. As shown in Fig. 3, the etching progress was monitored in real time at each process step using an optical microscope, and the completion of each etching step was evaluated by observing the color change of the structure.

Table 1 Etch gases and conditions for each layer.
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The measurements of the completed a-IGZO TFT array were performed by varying the gate voltage from − 35 V to + 40 V, with ground applied to the source electrode and 0.5 V to the drain electrode. The measurements were conducted using a probe station and Agilent 4156 C parameter analyzer.