Introduction

The escalating demand for faster, denser, and more energy-efficient memory technologies has grown rapidly in response to the exponential growth of data-intensive applications, particularly those driven by artificial intelligence (AI) and machine learning(ML). Minimizing Metal–Oxide–Semiconductor Field-Effect Transistors (MOSFETs) below 10 nm poses challenges, including excessive leakage power and quantum effects. Carbon Nanotube Field-Effect Transistors (CNTFETs) offer a promising solution by mitigating these drawbacks and exhibiting remarkable electrical properties such as large current density, substantial transconductance, minimal power consumption, reduced leakage power, and an excellent ION/IOFF ratio1. Carbon nanotubes (CNTs), with diameters as small as 1–6 nm, enable ballistic electron or hole transport, making them ideal for memory applications. CNTFET device performance is intricately linked to gate oxide thickness and dielectric constants2, particularly as device architectures continue to shrink, introducing quantum mechanical effects like tunneling and quantum confinement3,4,5,6. The increasing integration of Internet of Things (IoT) infrastructure in the healthcare industry underscores the need for innovative memory solutions7.

Static Random-Access Memory (SRAM) plays a significant role in embedded IoT devices due to its capability to store and retrieve data at high speeds8. Embedded SRAM is a critical component of system-on-chip (SoC) designs, finding applications in diverse fields such as intelligent smartphones, satellite technology, defense-related wireless sensors, and IoT devices9,10. The requirement for on-chip SRAMs with low power consumption and extended battery life is crucial, given their substantial impact on system performance and their dominant chip area, as highlighted by the International Technology Roadmap for Semiconductors (ITRS)11. In this context, our paper explores the essential role of SRAM in Very-Large-Scale Integration (VLSI) systems, emphasizing its significance for embedded applications12. The pressing need for portable devices to operate efficiently on minimal power has elevated the demand for low-power, high-performance SRAMs13,14. Considering that SRAMs significantly influence overall system speed due to their substantial footprint on the CPU, researchers are actively pursuing advancements in SRAM performance using CNTFET technology. This work contributes to the ongoing efforts to develop next-generation VLSI systems by harnessing the potential of CNTFETs for enhanced SRAM performance. CNTFET-based SRAMs possess enhanced thermal stability and reduced power consumption relative to their CMOS equivalents. The power consumption of CNTFET-based SRAM stays more efficient under varying temperature environments. The high thermal conductivity of carbon nanotubes, which exceeds that of silicon, enables CNTFETs to dissipate heat efficiently, hence minimizing the risk of thermal hotspots during operation. The read delay of 6 T SRAM is 5.9 ns (ns), and its power consumption is 10.054 nanowatt (nw), as shown in this article by Depak et al.15. The model we propose for the 6 T SRAM uses a tube diameter of 1.4877 nm (nm) and has a read delay of 6.231 picoseconds (ps) and a power consumption of 1.829 nw. In their paper16,17, L. Chang et al. and I.J. Chang et al. discovered that the read delay for the 6 T SRAM and 8 T SRAM structure configurations is 6.5 ns and 8 ns, respectively. The power consumption of the 6 T and 8 T SRAM cells is 12.458 nw and 17.58 nw, respectively. However, our proposed design demonstrates that the read delay for 8 T, 10 T, and 10 T (modified) SRAM is 5.775 ps, 9 ps, and 5.31 ps, respectively. The key contributions of this paper aspects are :

  • Comparative analysis of 6 T, 8 T, 10 T, and modified 10 T CNTFET-based SRAM under tube diameter and dielectric materials variations.

  • Assessment of read/write delays, power consumption, and PDP for different gate dielectrics & chirality.

  • Identification of optimal SRAM designs balancing stability, speed, and energy efficiency.

  • Insights into performance trade-offs across advanced CNTFET SRAM topologies.

Structures of CNTFET

Carbon nanotubes (CNTs) are cylindrical nanostructures of carbon atoms arranged in a unique hexagonal lattice. The carbon nanotube (CNT) contains two distinct chirality vectors, namely n and m. If the result of substituting the chirality vector (n-m) is an integer that can be evenly divided by 3, then the carbon nanotube (CNT) will exhibit metallic properties. Otherwise, it will exhibit semiconducting properties. The atomic structure of nanotubes is determined by their chirality (chiral vector, Ch) and chiral angle (θ). The expression, Ch = na1 + ma2 describes a chiral vector, where a1, a2, n, and m are lattice vectors, indices of chirality. The formula for determining the size of a carbon sphere18,19,20,21,22,23.

$${\text{Tube Diameter}},d = \frac{a}{\pi }\sqrt {n^{2} + nm + m^{2} }$$
(1)
$${\text{Chiral angle is}},\theta = \tan^{ - 1} \frac{{\sqrt {3m} }}{2n + m}$$
(2)

This article provides a comprehensive exploration of the profound impact of chirality on the properties of carbon nanotubes (CNTs)24, focusing on the classification and unique characteristics associated with different chiral indices (m, n). The chiral matrix, denoted as (Ch), the "roll-up matrix," is introduced as a key element in understanding the spiral nature and symmetry of CNTs. While symmetric carbon nanotubes are idealized, real-world scenarios often deviate due to the influence of defects on the mechanical characteristics of both genuine CNT structures and CNT-based composites. The concept of the chiral matrix explains its role in defining the size and symmetry of CNTs along their tube axis. Chiral indices, expressed as combinations of integers (m, n), not only characterize the magnitude but also the angle within the roll-up matrix of particular interest is the tunability of single-walled carbon nanotubes (SWCNTs) based on their chiral indices. The electrical characteristics of SWCNTs, including the bandgap, are intricately linked to their chiral configuration, rendering SWCNTs either metallic or semiconducting25,26. This tunability offers a wide range of possibilities for tailoring CNT properties to meet specific application requirements. Accurate characterization of the chiral features in synthesized CNT samples is emphasized, given that most synthesis processes yield a combination of chiral configurations27,28,29,30. The ability to fine-tune CNT properties based on chirality presents new avenues for tailored applications, positioning chirality as a critical aspect in designing and optimizing carbon nanotube-based materials24,25,31. Carbon nanotubes have exceptional mechanical strength, significant chemical stability, and durability under electrical stress32; hence, they minimize vulnerability to channel degradation. The quasi-one-dimensional structure of CNTs results in decreased defect formation relative to conventional silicon channels. Repeated cycling can induce electromigration at metal-CNT interfaces, generate traps in the gate dielectric, and cause charge trapping or dielectric breakdown, especially when high-κ materials are utilized as gate insulators33.

In this section Fig. 1 shows the two-dimensional view of the CNTFET structure. From the top side of this FET the Top view of the CNTFET is showed in Fig. 2.

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2D View of CNTFET.

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Top view of CNTFET.

Device parameter definition and default values for SRAM cell simulation

The chosen CNT tube diameters (1.0179–1.95575 nm) align with experimentally attainable ranges for semiconducting single-walled CNTs, as detailed in34,78 . The specified dielectric constants (3.9–30) are for real materials that may be utilized in nanoscale devices, such as SiO₂ (k = 3.9), Al₂O₃ (k ≈ 11) ,HfSiO4 (k ≈ 16), HfO₂ (k ≈ 25), ZrO₂ (k ≈ 30). These materials can be used as a gate dielectric to make CMOS based SRAM cell. These sets of parameters have been used in many past CNTFET modeling studies35 and make sure that the device behavior is simulated realistically at the 32 nm technology node. Table 1 represnts the device parameter of CNT for the simulation of this paper.

Table 1 Device parameter definitions and default values1,2.
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Schematic diagram of CNTFET based 6 T,8 T,10 T & 10 T(Modified) SRAM

In this section Figs. 3, 4, 5 and 6 shows the schematic representation of CNTFET based 6 T, 8 T, 10 T & 10 T (Modified) SRAM structures. Here, ‘PM’ represents the P-type CNTFET & ‘NM’ represents the N-type CNTFET.

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Schematic of CNTFET based 6 T SRAM cell.

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Schematic of CNTFET based 8 T SRAM cell.

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Schematic of CNTFET based 10 T SRAM cell.

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Schematic of CNTFET based 10 T(Modified) SRAM cell.

Adapting CNTFET-based 8 T SRAM memory cell to varied nano environments with tube diameter and dielectric manipulation

Write & read delay analysis of 8 T SRAM cell

Graphene is a variant form of carbon, whereas a carbon nanotube (CNT) is a cylindrical structure made from rolled-up graphene. Chirality can be employed to ascertain if a single-walled carbon nanotube (SWCNT) possesses metallic or semiconducting properties. The diameter of a single-walled carbon nanotube (SWCNT) may be determined based on its chirality, as indicated below36,37,

$${\text{D}}_{{{\text{cnt}}}} = \frac{{\text{Chiral vector }}}{{\uppi }}$$
(3)

Here a stand for graphene grid constant (a = 0.249 nm) , the diameter of the CNT channel is Dcnt , n & m is representation of the chirality vector . Expression relating threshold voltage (Vth) to energy bandgap (Eg) and Dcnt is given below3,4,5,

$${\text{ V}}_{{\text{threshold }}} = { }\frac{{{\text{a}} \times {\text{V}}_{{\uppi }} }}{{\surd 3{\text{ e D}}_{{{\text{cnt}}}} }} \approx \frac{{{\text{E}}_{{\text{g}}} }}{{2{\text{ e}}}}{ } \approx \frac{0.43}{{{\text{D}}_{{{\text{cnt}}}} { }\left( {{\text{nm}}} \right)}}$$
(4)

Here, \({\text{V}}_{{\uppi }}\) = Energy bond of the carbon = 0.3033 eV, \({\text{E}}_{{\text{g}}}\) = Energy band gap (spacing between the valence band & conduction band = 0.43 eV, e = charge of the electron = \(1.6 \times 10^{ - 19 } C\).

Figure. 8 shows Read delay vs Tube Diameter of CNT with various dielectric constants with various dielectric constants.

Figures 7 and 8 illustrate that both the write delay and read delay of 8T SRAM based on CNTFETs a decrease as the tube diameter increases. The delay exhibits a diminishing trend with bigger tube diameters as a result of a faster switching speed24. When there is a significant energy gap between the valence band and the conduction band, the process of electrons moving from the valence band to the conduction band is slower. By utilizing Eqs. (3 ~ 4), it is evident that the bandgap of CNTFET is inversely proportional to the diameter of the CNT . Hence, enlarging the tube diameter will reduce the bandgap of the CNTFET38,39. The device’s conductivity will be increased by the reduction of the bandgap39,40. The bandgap is defined as the energy difference between the valence and conduction bands. Increasing the diameter of the tube reduces the bandgap, causing the valence & conduction bands to approach one another. As the valence band and conduction band come closer together, the time required for electrons to move from the valence band to the conduction band decreases41. Consequently, conduction will be faster. Furthermore, when the diameter of the tube decreases, the bandgap expands, resulting in an increased separation between the valence and conduction bands42. As a result, the conduction will experience a delay. Hence, the bandgap of the tube is inversely proportional to its diameter. The conductivity of the tube is directly proportional to its diameter. Conversely, conductivity and delay have an inverse correlation43.

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Write Delay vs Tube Diameter of CNT.

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Read delay vs Tube Diameter of CNT.

By introducing materials with high dielectric constants into carbon nanotube (CNT) transistors, we might enhance the potential of molecular electronics. Dielectric materials play a crucial role in transistor architecture by functioning as insulating layers that separate the conducting components. They provide precise control of the flow of charge and allow for adjustments in device reliability37. Increasing the dielectric constant of the device leads to an increase in the drain current. It has been observed that using materials with a high dielectric constant helps decrease the concentration of the electric field44. Using a higher dielectric material in the gate can lead to an increase in capacitance and a decrease in the threshold voltage. A decreased dielectric constant can lead to diminished capacitance and an elevated threshold voltage45. The dielectric constant of the material is directly related to the gate capacitance, whereas the gate capacitance is inversely proportional to the threshold voltage of the device. Using a material with a higher dielectric constant will result in an increase in the gate capacitance and a drop in the threshold voltage. This will lead to an increase in the device’s switching speed45. Figures 9 and 10 indicate that there is a decrease in write and read delay when the dielectric constant value improves. The properties of the read operation closely resemble those of the write operation. Nevertheless, in the case of the 8T CNTFET-based SRAM, we have observed that the read operation has a greater delay compared to the write operation24. By increasing the diameter of the CNTs from 1.0179 nm to 1.95575 nm and using hafnium silicate as a dielectric material, the write delay decreases by 12.16% and the read delay decreases by 12.20%, which are virtually equal. When the tube diameter is 1.4877 nm and the dielectric constant ranges from 3.9 to 30, the write delay decreases by 15.13% and the read delay decreases by 14.41%46.

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Write Delay vs Tube Diameter of CNTFET based SRAM cell topologies.

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Read delay vs Tube Diameter of CNTFET based SRAM cell topologies.

In the previous section, we observe the impact of different tube diameters on CNTFET-based SRAM. Our analysis revealed that increasing the diameter of the tube leads to a decrease in delay. This section presents an analysis of the performance of several types of SRAMs, including 6T, 8T, 10T, and modified 10T. The study compares the write delay, read delay, power consumption, PDP (power delay product), and EDP (energy delay product). Figure 9 and 10 demonstrate that 6T SRAM has lower write and read delay compared to 8T SRAM, mostly because of the extra transistor present in 8T SRAM. The 10T SRAM cell has an additional four transistors in comparison to the 6T version, rendering it the most expansive and complex SRAM cell design43. Unlike the 6T and 8T designs, this architecture offers improved reliability for both reading and writing data and is less susceptible to interference. The revised 10T SRAM cell comprises vertically arranged P-CNTFETs with a pull-up configuration and N-CNTFETs with a pull-down interconnection45. Both of these transistors are in a permanently activated state. The improved 10T SRAM cell incorporates distinct pathways for both read and write operations, resulting in decreased delay compared to previous types of SRAMs47.

Figures 9 and 10 illustrate the significant fluctuations in delay for different types of SRAM and tube widths, utilizing a dielectric constant of 3.9. The write delay decreases by 11.71% for 6T SRAM, 30.22% for 8T SRAM, 21.44% for 10T SRAM, and 30.06% for 10T (modified) SRAM when the tube diameter changes from 1.0179 nm to 1.95575 nm. The read delay for 8T, 10T, and 10T (modified) SRAM drops by 32.16%, 22.24%, and 51%, respectively, when the tube width is increased from 1.0179 nm to 1.95575 nm. These findings suggest that the tube width significantly influences the switching ratio of 10T (modified) SRAM. Furthermore, the read delay decreases more rapidly than the write delay.

Power consumption analysis of 8 T SRAM Cell:

According to the data displayed in Fig. 11, the simulation of 8T CNTFET-based SRAM demonstrates that an increase in tube diameter leads to an expansion in the SRAM’s overall power consumption. Conversely, an increase in the dielectric constant results in a decrease in the SRAM’s power consumption. Figure 11 illustrates that for carbon nanotubes (CNTs) with a diameter less than roughly 1.5 nm, the power consumption remains almost constant. However, if the diameter of the CNT exceeds 1.5 nm, power consumption begins to rise due to an increase in leakage current. We can also observe that having a higher dielectric constant contributes to greater power consumption. The threshold voltage drops as the dielectric constant and tube diameter rise48.

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Power consumption vs Tube Diameter for different Dielectric constant.

As a result, CNTFET gate leakage rises. This causes the cell’s requirements for power consumption to expand49. It is possible to represent the on-current of the CNTFET using the notation,

$${\text{ I}}_{{{\text{CNTFET}}}} = \frac{{{\text{Ng}}_{{\text{CNT }}} \left( {{\text{V}}_{{{\text{dd}}}} { } - {\text{ V}}_{{{\text{th}}}} } \right)}}{{1{ } + {\text{g}}_{{{\text{CNT}}}} {\text{L}}_{{\text{s}}} {\uprho }_{{\text{s}}} }}$$
(5)

Here, gCNT = Transconductance of the CNTFET, N = Number of CNT, Ls = Source length, ρs = The source resistance per unit length of doped CNT, Vth = Threshold Voltage, Vdd = Supply voltage.

The equation for the CNTFET’s ON current shows that it depends on several elements, including transconductance, CNT number, source length, and so on. It is well known that the CNTFET bandgap decreases with tube diameter. A noteworthy fact is that a CNTFET’s bandgap is inversely linked to its transconductance43. Therefore, increasing the tube diameter will lower the CNTFET’s bandgap energy, which will enhance its transconductance. Furthermore, we may examine the impact of transconductance on the current of the CNTFET by utilizing Eq. (5), which demonstrates a direct proportionality between the two. Due to the presence of on-state current, there is a corresponding increase in the leakage current detected in the off-state current of the CNTFET. The source of the leakage current may be attributed to ambipolar transport and gate-induced drain leakage, both resulting from electron tunneling over the drain side46. Based on this information, it is probable that a greater impact of leakage current is the cause of the higher power consumption seen when using a wider tube diameter38,50,51. Enhancing the diameter of the CNT enhances the conductivity of the device. As the diameter of carbon nanotubes (CNTs) increases, their conductivity increases, reducing their power handling capability. The negative link between tube diameter and Vth is the cause of this phenomenon52. A decrease in the threshold voltage (Vth) increases the required power when the diameter is very large38. By modifying the diameter of carbon nanotubes (CNT) from 1.0179 nm to 1.4877 nm and employing hafnium oxide as the dielectric material, the overall power consumption is increased by 80.69%. Nevertheless, when the diameter of the tube is precisely 1.95575 nm and the dielectric constant ranges from 3.9 to 30, the resulting increase is just 2.17%.

Figure 12 depicts the power consumption of several SRAMs in tubes with varying sizes. The presence of more transistors increases the power consumption of the typical 10T SRAM. A standard 10T SRAM uses a transmission gate to gain access to the storage node37. The large parasitic capacitance of the transmission gate increases both the circuit’s access time and power consumption. Conversely, SPD (split pull-down) SRAM displays less parasitic capacitance, necessitating a shorter access time and reduced power consumption52. Based on this curve, it can be inferred that the 6T CNTFET-based SRAM consumes the lowest power among other types of SRAM, as indicated in reference53. To enhance stability, a 10T SRAM is employed. However, this results in the highest power consumption among all components of the device, which might potentially lead to a degradation in performance54.

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Power consumption vs Tube diameter of CNTFET based SRAM Cell topologies.

Write & read PDP analysis of 8T SRAM cell:

The performance of CNT-based devices in terms of PDP is highly dependent on the diameter of the tubes and the dielectric constant. Bandgap, conductivity, capacitance, leakage current, and power consumption are among the device features that may be enhanced by modifying these parameters.

Figures 13 and 14 illustrate the correlation between the write and read PDP and the tube diameter, as well as the dielectric constant. With a tube diameter of 1.0179 nm and a dielectric constant of 3.9, the write PDP is 4.1016132 zeptojoules (zj), and the read PDP is 4.2262449 zj. The power dissipation per unit area (PDP) for writing is 4090.789887 zeptojoules (zj), while for reading it is 890.7081 zj, given a tube diameter of 1.95575 nm and a dielectric constant of 30. The statement suggests that changes in the diameter of the tube, especially when it is greater, and the dielectric constant significantly impact the PDP. Carbon nanotubes with a smaller diameter reduce delay times because their smaller cross-sectional area leads to lower on-current55. As a result, PDP may decrease CNTs with reduced diameter exhibiting improved electrostatic manipulation, facilitating their activation and deactivation by the application of a gate voltage. Consequently, the rate at which power is dissipated, known as the power dissipation rate (PDP), decreases56. The reduced parasitic capacitance of smaller-diameter CNTs results in a decrease in the required switching charge. As a result, the power dissipation product (PDP) is reduced57. At a diameter of around 1.5 nm, carbon nanotubes (CNTs) exhibit many modes of conduction, including the radial respiratory mode and higher-order transverse modes. These modes can result in enhanced dispersion and reduced mobility. Delayed reactions and greater power usage may result in an elevated device’s PDP58

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Write PDP vs Tube diameter of CNTFET based SRAM cell topologies.

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Read PDP vs Tube diameter of CNTFET based SRAM Cell topologies.

Figure 13 illustrates the correlation between tube diameter and PDP for different types of SRAMS. The graph shows that the PDP values for tube diameters of 1.0179 nm are 2.8764093 zj, 4.1016132 zj, 13.508268 zj, and 5.758767 zj for 6 T, 8 T, 10 T, and 10 T (modified), respectively. Furthermore, Fig. 14 illustrates that the power dissipation (PDP) values for the 8 T, 10 T, and 10 T (modified SRAM) are 4.2262449 zj, 15.8355 zj, and 8.339727 zj, respectively. A smaller diameter of the carbon nanotube field-effect transistor (CNTFET) will lead to a higher power dissipation during the read operation compared to the write operation. The graph also shows that a tube diameter of 1.95575 nm results in PDP values of 990.47 zj, 968.71 zj, 1291.19 zj, and 866.73 zj for 6 T, 8 T, 10 T, and 10 T (modified), respectively. Furthermore, the recorded power dissipation (PDP) values are 992.136 zj, 1498.23 zj, and 873.34 zj for the 8 T, 10 T, and 10 T (modified SRAM) configurations, respectively. A smaller tube diameter for the CNTFET will lead to a higher read power-delay product (PDP) compared to the write PDP.

Write & read EDP analysis of 8T SRAM cell

This study presents a comprehensive analysis of the energy delay product (EDP) in carbon nanotube field-effect transistor (CNTFET)-based SRAM cells, with a specific emphasis on the influence of tube diameter and dielectric constant. Figures 15 and 16 depict the correlations between write EDP and tube diameter, as well as read EDP and tube diameter. Significantly, the effective diameter parameter (EDP) remains rather stable for tube sizes below a certain threshold. However, as the diameter exceeds 1.4 nm, the EDP for writing purposes begins to rise. Moreover, greater dielectric constants lead to larger write and read EDP values, where a dielectric constant of 80 produces five times as much EDP as a value of 3.9.

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Write EDP vs Tube diameter of CNTFET based SRAM cell topologies.

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Read EDP vs Tube diameter of CNTFET based SRAM cell topologies.

By changing tube diameter results as a reduction of 4.94% in write EDP and a drop of 5.86% in read EDP. The decline can be attributable to the fluctuating dielectric constant, which clearly demonstrates its influence on EDP. Figures 15 and 16 expand the investigation to several types of SRAM cells, demonstrating that the write and read EDP values stay rather consistent for smaller tube sizes across all SRAM types55. Nevertheless, larger tube diameters regularly result in greater EDP values. It is worth mentioning that the traditional CNTFET-based 10T SRAM has the highest write and read EDP values, which are over three times higher than those of other SRAM types when using bigger tube sizes. This work offers significant insights into the intricate correlation among tube diameter, dielectric constant, and EDP in CNTFET-based SRAM cells56. The findings support the current endeavours to enhance energy efficiency in nanoelectronics memory systems. Table 2 were compiled from previously published and validated works employing different device technologies and simulation environments. Hence, the comparison is primarily qualitative, intended to show general performance trends among advanced transistor technologies. Despite variations in technology nodes and modeling parameters, the consistent reduction in delay and power consumption observed in CNTFET-based SRAM supports the superior intrinsic electrical characteristics of CNT channels, including high carrier mobility and near-ballistic transport. Therefore, the presented comparison serves as a literature-based benchmark that validates the potential of CNTFETs for next-generation high-speed, low-power memory systems. Table 2 represnts the comparative analysis between different technology based SRAM cell is given below :

Table 2 Comparative analysis of different technologies SRAM.
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CNTFETs, with their high carrier mobility, low leakage, and excellent electrostatic control, hold great promise for next-generation electronics. Potential applications include high-performance and low-power computing, advanced memory designs (SRAM/DRAM)60, flexible and transparent devices, and RF/analog circuits. These attributes position CNTFETs as a key technology for post-silicon electronics and emerging nanoelectronic products62,63.

Table 3 represents the comparison of different types of SRAM used in this study with higher & lower tube diameter of the CNT with a dielectric constant of SiO2 with other previous studies.This study investigates the cell-level performance of CNTFET-based SRAMs using various tube diameters and dielectric constants. However, scaling up to bigger memory arrays or smaller technology nodes runs into more problems, such as interconnect parasitics, IR disruption, peripheral circuit overhead, and CNT unpredictability67,68. These things can change how fast, powerful, and stable something is.

Table 3 Performance comparison of CNTFET-based SRAM cells (dielectric constant = 3.9).
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In further research, we intend to investigate bigger SRAM arrays through layout-aware simulations that incorporate connection and supply impacts. We will also do a variability analysis and look at scaling to more advanced technology nodes (16 nm and 7 nm) to see the way the architecture works and the amount of space it takes up, as well as the reliability of it as it is for system-level integration69,70,71,72.

To make sure the presented findings were accurate, we ran each simulation several times under the same conditions using the Stanford CNFET model in Cadence Virtuoso. The changes in important performance parameters, including delay, power, and PDP, that occurred were within ± 1–3%. This is because nanoscale simulations include small numerical and parameter fluctuations that are expected. The research additionally explored the way variations in CNT chirality, shifts in threshold voltage, and uncertainty in process parameters may affect the results. These findings demonstrate that the observed performance patterns are stable and statistically significant.

Static noise margin (SNM) OF CNTFET based SRAMs

The Static Noise Margin (SNM) is a very important measurement for figuring out how stable and strong SRAM cells are. SNM is the highest voltage change that an SRAM cell can handle without affecting the logic state of the data it stores69. The SNM of CNTFET-based SRAM cells has improved than that of conventional CMOS SRAM cells because Carbon Nanotube Field-Effect Transistors have built-in benefits such high carrier mobility, near-ballistic transport, and precise threshold voltage control. The butterfly curve approach is the most common way to look at SNM73,74. In this method, the voltage transfer characteristics (VTC) of the two cross-coupled inverters are displayed, and the largest square that can fit between the curves is the SNM75.

Figure 17A illustrates the N-curve analysis of the 6 T CNTFET-based SRAM, while Fig. 17B depicts the N-curve analysis of the same SRAM utilizing the 45-degree method, featuring a tube diameter of approximately 1.955 nm for the CNT and ZrO₂ as the dielectric material.

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(A) N-Curve of 6 T CNTFET based SRAM (B) N-Curve of 6 T CNTFET based SRAM using 450 method.

Figure 18A illustrates the N-curve analysis of the 8 T CNTFET-based SRAM, while Fig. 17B depicts the N-curve analysis of the same SRAM utilizing the 45-degree method, featuring a tube diameter of approximately 1.955 nm for the CNT and ZrO₂ as the dielectric material.

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(A) N-Curve of 8 T CNTFET based SRAM (B) N-Curve of 8 T CNTFET based SRAM using 450 method.

Figure 19A illustrates the N-curve analysis of the 10 T CNTFET-based SRAM, while Fig. 19B depicts the N-curve analysis of the same SRAM utilizing the 45-degree method, featuring a tube diameter of approximately 1.955 nm for the CNT and ZrO₂ as the dielectric material. Figure 20A illustrates the N-curve analysis of the 10 T (modified) CNTFET-based SRAM, while Fig. 20B depicts the N-curve analysis of the same SRAM configuration utilizing the 45-degree method, featuring a tube diameter of approximately 1.955 nm for the CNT and ZrO₂ as the dielectric material.

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(A) : N-Curve of 10 T CNTFET based SRAM (B) : N-Curve of 10 T CNTFET based SRAM using 450 method.

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(A) : N-Curve of 10 T (modified) CNTFET based SRAM (B) : N-Curve of 10 T (modified) CNTFET based SRAM using 450 method.

Table 4 presents a comparative overview of SRAM implementations based on different transistor technologies, including CNTFET, FinFET, and TFET. The CNTFET-based SRAM results are obtained from the simulations performed in this work using a consistent 32 nm technology framework. Table 0.4 represnts the static noise margin (SNM) among different SRAM technologies:

Table. 4 SNM comparison between different technologies SRAM.
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Conclusion

This study investigates the design attributes of carbon nanotubes (CNTs) to evaluate their performance measures. Furthermore, the assessment of CNTFET-based 8T SRAM architectures is performed utilizing both the conventional simulation setup and modified versions of this configuration. The simulation is performed via CADENCE (Virtuoso) software, employing a 32 nm CNTFET channel diameter. At first, we created an 8T SRAM utilizing CMOS and CNTFET technology, and then we assessed the SRAM’s performance. In order to assess the efficiency of an 8T SRAM utilizing CNTFET technology, we have measured the time it takes for data to be written and read, the amount of power consumed, as well as the product of power and delay (PDP) and the product of energy and delay (EDP). These measurements were obtained by altering various parameters of the CNTFET. In the preliminary phase, we performed an examination of this SRAM by employing different tube sizes and dielectric constants. The experiment revealed that employing zirconium oxide (ZrO2) as the dielectric material in conjunction with a larger tube diameter led to a decreased delay. The reason for this is that a bigger tube diameter exhibits more conductivity, whereas a higher dielectric constant amplifies the drain current of the device. Nevertheless, it is important to acknowledge that this also results in increased leakage current and power consumption. By altering the diameter of the tube within the range of 1.0179 nm to 1.95575 nm, while also changing the dielectric constants, the latency for writing and reading decreased by around 10% to 30%. Nevertheless, while dealing with larger tube diameters, the influence of utilizing various dielectric materials becomes less substantial. Finally, this research presents a comparative examination of several varieties of SRAM. Here we have conducted an investigation of the performance of 6T, 8T, 10T, and 10T (modified) SRAM. The initial comparison is centred around the variation in tube diameter, in which the 10T (modified SRAM) exhibits enhanced delay performance of 30.06% in write operation and 51% in read operation when compared to other SRAMs. Also the planar variability in CNT diameter and doping, precise CNT placement, contact formation, interconnect parasitics, and thermal management are critical factors for reliable and scalable memory implementations.

Future work

Although this work focuses on the intrinsic performance evaluation of CNTFET-based SRAM architectures under nominal conditions, it does not include Process, Voltage, and Temperature (PVT) variation analysis. PVT variations significantly affect stability, noise margins, and yield in nanoscale memory design. Therefore, as part of future research, a comprehensive study incorporating Monte Carlo simulations and corner-based PVT analysis will be conducted to evaluate the robustness and reliability of CNTFET-based SRAM cells under practical operating conditions.