Introduction

The down scaling of field-effect transistor (FET) dimensions has been continuously driven the development of integrated circuits1,2,3. However, as the complexity of the process increases and the limit of minimum size is approached, the increase in leakage current and subthreshold swing (SS) caused by short-channel effects leads to a significant rise in device power consumption4,5,6,7. Therefore, there is an urgent need to develop new gate dielectric materials that are capable of enhancing gate control and suppress the short-channel effects8,9.

Ideal dielectrics should possess a high dielectric constant (κ) and a wide bandgap (Eg)10,11. On the one hand, a high-κ value can offer a larger gate capacitance, thus enhance gate control ability, lower the operating voltage and dynamic power consumption of the device. On the other hand, a wide bandgap can provide sufficient band offset to reduce leakage current, thereby increasing the current on/off ratio and reducing the static power consumption of the device12,13,14. Nevertheless, achieving both a high-κ and a wide bandgap in one dielectric remains challenging. In typical inorganic dielectrics, the dielectric constant and bandgap often exhibit an inverse relationship, such as SiO2 (κ ~ 3.9, Eg ~ 9 eV) and TiO2 (κ ~ 80, Eg ~ 3.4 eV)5,15,16. This is mainly because the electronic contribution to the dielectric constant has a prominent inverse relationship with the bandgap. Therefore, to obtain a high dielectric constant while maintaining a wide bandgap, one needs to focus on the ionic contribution to the dielectric constant, which is related to the bond strength of the material17,18. Therefore, developing materials composed of elements with large electronegativity differences, small atomic sizes, and short bond lengths is an effective strategy for achieving dielectrics with both high-κ value and wide bandgap.

In this work, we report a dielectric of KBe2BO3F2 (KBBF), which exhibits both a high bulk dielectric constant (63) and a wide bandgap (>8 eV). Among its constituent elements, fluorine has the highest electronegativity and the smallest ionic size among all anions. Additionally, KBBF features short chemical bond lengths, providing a foundation for its high dielectric constant and wide bandgap. As a result, KBBF demonstrates an low leakage current (<10−6 A cm−2) at an equivalent oxide thickness (EOT) of 0.62 nm and a high gate voltage of 15 V, and is predicted to work stably for 10 years at 6.6 V. The inert fluorine atom-terminated surface of KBBF enables its integration with two-dimensional (2D) semiconductors via van der Waals (vdW) forces19,20,21, creating high-quality dielectric/channel interfaces. MoS2 FETs gated by KBBF exhibit a maximum on/off current ratio exceeding 109, an ultimate SS of 60 mV dec−1. Additionally, we utilize KBBF to fabricate high-gain inverters, demonstrating its potential in advanced integrated circuit applications.

Results

Preparation and structure of KBBF thin layer

Unlike other typical 2D vdW materials, KBBF crystal features of a six-membered ring network structure of Be2BO3F2 and K ions distributed between the layers. The sharp X-ray diffraction (XRD) peaks confirm the high crystallinity of our KBBF crystal with a lattice parameter of a = b = 4.427 Å and c = 18.744 Å (Supplementary Fig. 1). To integrate the 2D dielectric KBBF with 2D channel materials, we prepared KBBF thin layers via mechanical exfoliation from the bulk crystal using Scotch tape, as illustrated in Fig. 1a. For more efficient preparation, we employed the sliding layer method22. For brief, a few KBBF crystals were sandwiched between two pieces of weighing paper and a plastic rod was then rolled gently in one direction on the surface to apply a shear force on the crystals, causing sliding between adjacent layers and enhancing exfoliation. This method enables the preparation of KBBF thin layers with varying thicknesses (Supplementary Fig. 2), and the great surface uniformity of KBBF was also demonstrated by the scanning electron microscope (SEM) image and energy dispersive spectroscopy (EDS) mapping of K and F elements (Supplementary Fig. 3).

Fig. 1: Preparation and characterization of KBe2BO3F2 (KBBF) thin layers.
Fig. 1: Preparation and characterization of KBe2BO3F2 (KBBF) thin layers.The alternative text for this image may have been generated using AI.
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a Schematic illustration of the preparation processes. b Optical microscope (OM) and atomic force microscope (AFM) images of the KBBF thin layer. Inset: the height profile along the white dashed line. Scale bars, 2 μm in OM image and 1 μm in AFM image. c High-resolution transmission electron microscope (HRTEM) image of the KBBF thin layer. Scale bar, 1 nm. Inset: the TEM image of the KBBF thin layer. Scale bar, 1 μm. d Atomic schematic of a KBBF/MoS2 heterointerface. e Cross-sectional HRTEM image of the KBBF/MoS2 heterostructure on SiO2 substrate. Scale bar, 2 nm. Clean, flat interfaces can be identified. Right: enlarged HRTEM images of KBBF and MoS2. Scale bar, 1 nm. f Cross-sectional TEM image and corresponding electron energy loss spectroscopy (EELS) mapping of the elements Mo, Be, B, O, F, and Si. Scale bar, 10 nm.

The optical microscopy (OM) and atomic force microscopy (AFM) images in Fig. 1b reveal that the as-exfoliated KBBF thin layer has a smooth and uniform surface, with a minimum thickness of 2 nm, corresponding to around three atomic layers of the KBBF crystal. High-resolution transmission electron microscopy (HRTEM) image and selected-area electron diffraction pattern demonstrate the high-quality single-crystal nature of the KBBF, with very limited defects in the probed areas, which is also demonstrated by the EDS mapping (Fig. 1c and Supplementary Fig. 4). The interplanar spacing of the periodic atomic distribution d(−120) = 2.21 Å, consistent with the unit cell parameters of KBBF. Cross-sectional TEM images, obtained cutting the sample with a focused-ion beam, reveal that both the KBBF dielectric and the underlying MoS2 channel show typical layered structures with clean and flat surfaces. The flat and clear interface demonstrates that the integration process does not damage the structure of 2D materials, which is crucial for effective gate control and device performance. Additionally, an identified vdW gap between the KBBF and MoS2 will reduce the tunneling probability of charge carriers and help minimize the gate leakage current (Fig. 1d, e). The electron energy loss spectroscopy (EELS) mapping in Fig. 1f confirms the uniform distribution of the characteristic elements in each layer, aligning well with the stacked two-layer materials.

Dielectric properties of ultrathin KBBF

For investigating the dielectric properties of KBBF thin layer, we fabricated the metal–insulator–metal (MIM) parallel-plate capacitor. In this structure, the KBBF layer is sandwiched by an Au-coated SiO2/Si substrate and a top Au electrode (Fig. 2a, b). Figure 2c presents that the measured capacitance density remains stable with changes in voltage and frequency, indicating that there are almost no deep-level impurities and structural defects in the crystal and the potential of KBBF for high-frequency applications. The specific capacitance–voltage (C–V) and capacitance–frequency (C–f) curves of KBBF with different thickness was shown in Supplementary Fig. 5. According to the test results, the dielectric constant value ε of KBBF can be calculated by the formula: ε = Ct/Aε0, where C, t, and A are the capacitance, thickness and effective area of the KBBF, respectively, and ε0 is the vacuum dielectric constant. The thickness dependence of dielectric constant obtained from calculations were shown in Fig. 2d. It can be seen that the KBBF with a thickness of 12 nm has a high dielectric constant of 26.5, and the relationship between the dielectric constant and thickness aligns well with the dead layer model in high-κ capacitors23,24. While there is still debate about whether there is a thickness-related suppression of the dielectric constant on the surface of high-κ dielectric materials, the presence of a low interfacial capacitance region, commonly referred to as the dead layer between the electrode and the dielectric material, which is in series with the bulk capacitance, reduces the overall capacitance and leads to a decrease in the effective dielectric constant (Supplementary Fig. 6a). The fitting of the dead layer model can be performed according to formula: t/ε = t/εbulk + D, where εbulk is the bulk dielectric constant of the dielectric material, and D is a constant related to the interfacial dead layer. According to the fitting results, εbulk ≈ 63 and D ≈ 0.353 can be extracted, indicating that KBBF has excellent quality and the characteristic of a high dielectric constant (Supplementary Fig. 6b). In addition, considering the presence of vdW gap between the electrode and KBBF, the experimentally measured capacitance incorporates the contribution from the vdW gap. We have therefore attempted to deduct this specific capacitance component, as shown in Supplementary Fig. 7. Based on the calculation formula for series capacitance, we established a functional relationship between the measured capacitance and KBBF thickness. The fitting results indicate that, after excluding the capacitance contribution of the vdW gap, the dielectric constant of KBBF is determined to be 63, with the thickness of vdW gap measured at 0.353 nm. This result is consistent with the fitting outcome derived from the dead layer model, which verifies that the dead layer in this work originates from the vdW gap between the electrode and KBBF, and that the intrinsic dielectric constant of KBBF is 63. The EOT of KBBF with different thicknesses were shown in Fig. 2d. Due to the large dielectric constant, the minimum measured EOT can be calculated as 0.25 nm (t = 4 nm) according to the formula EOT = 3.9t/εKBBF.

Fig. 2: Dielectric properties of KBBF thin layers.
Fig. 2: Dielectric properties of KBBF thin layers.The alternative text for this image may have been generated using AI.
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a The structure diagram and b a false-coloured scanning electron microscope (SEM) image of the metal–insulator–metal (MIM) device. Scale bar, 5 μm. c Voltage-dependent capacitance density for MIM devices of 12 nm-thick KBBF layer at five different frequencies. Inset, frequency-dependent capacitance density at four different voltages. d Dielectric constant and equivalent oxide layer thickness (EOT) as a function of various KBBF thickness measured from MIM capacitors. The gray line is the fitted curve according to the dead layer model. e Bandgap of KBBF obtained from density functional theory (DFT) calculation. f Bandgap versus dielectric constant of typical dielectrics5,9,10,12,13,15,19,29,30,31,32,33,34,35,36,37,57,58,59,60. The dashed black line serves as a guide to illustrate the inverse proportionality between these two properties. g Time-dependent dielectric breakdown (TDDB) versus stress voltage characteristics of KBBF, where the black dash-line represents the lifetime prediction. Inset: Time-dependent breakdown curves of KBBF at various voltage stresses.

An ideal gate dielectric must possess a wide bandgap to guarantee a sufficiently high energy barrier, thereby reducing leakage current to negligible levels. We calculated the bandgap of KBBF to be 8.03 eV using the HSE06 functional within the framework of density functional theory (DFT) (see “Methods” for detailed computational details), which is consistent with literature reports (~8.31 eV)25. Generally, a large band gap will cause a low electronic contribution to the dielectric constant, thus making the band gap inversely proportional to the dielectric constant, as shown in Fig. 2f. However, KBBF simultaneously exhibits the characteristics of high dielectric constant and wide band gap. This is mainly due to its large atomic electronegativity difference and small chemical bond length, which enhances the ionic contribution in the dielectric constant (Supplementary Figs. 8 and 9).

The wide bandgap and high crystal quality make KBBF have an enhanced EBD and reduced leakage current (Jleak), which are critical parameters of advanced FETs to improve reliability and reduce power consumption. To describe the breakdown characteristics of the KBBF more accurately, we conducted a systematic ramped voltage stress test, which is a well-known method for evaluating the breakdown properties of dielectric materials26. Supplementary Fig. 10 presents the statistical results of the EBD of KBBF with different thicknesses (5–30 nm) under varying temperatures (150–350 K) and sweep rates (0.1–1 V s−1). It can be observed from the figure that the EBD of KBBF decreases slightly with increasing temperature and decreasing sweep rate. This phenomenon is mainly attributed to two factors: on one hand, the efficiency of electron energy accumulation in the material improves with rising temperature, making it easier to form breakdown paths; on the other hand, a slower sweep rate allows more time for charge injection, defect activation, or thermal accumulation to occur, thereby reducing the breakdown threshold. For the sample with a thickness of approximately 5 nm, it exhibits an EBD of about 28.4 MV cm−1 at a temperature of 150 K and a sweep rate of 1 V s−1. Even at room temperature, its EBD still exceeds 26 MV cm−1, which is more than four times that of the breakdown field strengths of SrTiO3 and SiO2 reported in the literature24,27. In addition, the measured leakage current of KBBF remains below 10−6 A cm−2 before the breakdown occurs, far below the low-power limit (1.5 × 10−2 A cm−2) and standard complementary metal–oxide–semiconductor gate limit (10 A cm−2) even when the EOT is less than 1 nm28. Furthermore, we evaluated the electrical reliability of KBBF by measuring the time to device failure under constant voltage stress, a characteristic metric defined as time-dependent dielectric breakdown (TDDB). Figure 2g summarizes the stress-dependent leakage current breakdown transients of a 10 nm-thick KBBF nanosheet under various test voltages. Data fitting further predicts that the nanosheet can achieve a 10-year long-term lifetime at an operational voltage of 6.6 V. Compared with the reported dielectric materials applied in state-of-art silicon and 2D semiconductor technologies, the KBBF crystals demonstrate the high breakdown strength at different dielectric constant (Supplementary Fig. 11)7,9,10,12,13,15,24,29,30,31,32,33,34,35,36,37,38,39,40,41. The key features of the gate insulator, namely bandgap, dielectric constant, and EBD, are summarized in Supplementary Table 1. It should be noted that Be is slightly toxic. Materials with the same structure but free of Be can also be explored as dielectric materials. However, the excellent dielectric properties and electrical stability of KBBF still make it a highly promising insulating material for high-performance 2D devices.

High-performance 2D FETs with KBBF dielectrics

To assess the electrostatic control capability of KBBF in 2D electronic devices, we integrate the KBBF thin layer onto 2D semiconductors to construct the top-gated 2D FETs and evaluate their device performance. In these FETs (Fig. 3a), MoS2 serves as the channel material, Bi/Au electrode were used to minimize contact resistance42, and the KBBF layer was positioned above the MoS2 as the gate dielectric (see “Methods” for details), the OM picture of the prepared FET was shown in Fig. 3b. For the dielectric and semiconductor stacks, band alignment is crucial for achieving small SS, minimal leakage current, and enhanced electrical stability in FETs. According to DFT calculations and ultraviolet photo-electron spectroscopy (UPS) measurements, ultrathin KBBF nanosheets have a wide bandgap of up to 8.03 eV, much larger than that of monolayer MoS2 (~1.78 eV). This substantial difference creates pronounced energy band offsets between the KBBF dielectric and the MoS2 channel, with offsets of 3.57 eV for the conduction band minimum and 2.61 eV for the valence band maximum (Fig. 3c and Supplementary Fig. 12). These values far exceed the threshold (> 1 eV) required for high-quality gate dielectrics, thereby effectively preventing electrons or holes from tunneling through the dielectric via direct tunneling or FN tunneling to induce substantial leakage current, which contributes to the development of low-power-consumption and high-performance devices12,43,44.

Fig. 3: KBBF dielectrics for high-performance 2D transistors.
Fig. 3: KBBF dielectrics for high-performance 2D transistors.The alternative text for this image may have been generated using AI.
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a A schematic of the top-gated MoS2 FET with KBBF dielectrics. S, D, and G represent the source, drain, and gate, respectively. Vds, Ids, Vbg, Vtg represent the source-drain voltage, source-drain current, back-gate voltage, and top-gate voltage, respectively. b The OM image of a top-gated MoS2 FET. Scale bar, 10 μm. c Band alignment between KBBF and MoS2. The band offsets were larger than 2 eV for both the conduction band minimum and valence band maximum. d Calculated density of states (DOS) of MoS2 and KBBF/MoS2 heterostructure. No defect levels introduced by KBBF in MoS2. e Typical transfer characteristic curves and leakage current (gray line) of the device. Inset: corresponding hysteresis width. f Subthreshold swing (SS) versus Ids extracted from the transfer curves. The dashed line marks Boltzmann limit. g The statistical plot of SS and hysteresis for ten MoS2 FETs with KBBF as dielectric. h Transfer characteristics of the FET under different Vbg from 0 to 20 V with 5 V step. i Out characteristic curves of MoS2 FET with Vbg = 20 V. j Negative bias-temperature instability of the MoS2 FET at 350 K and Vtg, stress = −2 V.

The typical transfer characteristics curves of KBBF/MoS2 FETs at room temperature and a sweep rate of 1 V s−1 were depicted in Fig. 3e, showcasing a remarkable on/off current ratio exceeding 109 and a low gate leakage current. The ideal heterointerface, characterized by minimal defects, enables the device to achieve good performance with a small hysteresis. We performed transfer characteristic measurements on the devices at different sweep rates and temperatures, and extracted the corresponding hysteresis widths, as shown in Supplementary Fig. 13. It can be observed that the devices exhibit excellent switching characteristics under all tested conditions. The hysteresis width increases slightly with the rise in temperature and the decrease in sweep rate, the maximum hysteresis is 35 mV and 12 mV at sweep rates of 0.1 V s−1 and 1 V s−1 at room temperature, respectively. More importantly, the channel current exhibits a sharp rise with a low threshold slope of 60 mV dec−1, we can identify that the SS can remain close to the Boltzmann thermionic limit over three orders of magnitude (Fig. 3f). To verify the reliability of KBBF as the dielectric, we fabricated ten FETs with the same procedure. The specific transfer characteristic curves of ten MoS2 FETs were shown in Supplementary Fig. 14, and all the devices exhibit excellent on/off characteristics and low gate leakage current. Figure 3g summarizes the SS, on/off ratio, and hysteresis of all devices. It can be seen that most devices are located within the region of low SS and low hysteresis, the average SS, on/off ratio, and hysteresis are 64.5 mV dec−1, 4 × 108, and 9.1 mV, respectively. This performance highlights the good electrostatic control and interface quality of the KBBF dielectric. Supplementary Fig. 15 illustrates the output characteristics curves of the device. The linear behavior of Ids−Vds curves at low bias confirms the Ohmic contact and effective current control. The electrical performance of the device can be further modulated through dual-gate operation. When a back-gate voltage is applied, the channel region not dominated by the top gate is activated, leading to a significant increase in channel current and a leftward shift in the threshold voltage (Fig. 3h). In addition, the maximum output current of the FET is enhanced by threefold with the incorporation of the back gate (Fig. 3i).

The performance of 2D semiconductors with atomic-scale thickness is highly sensitive to interface defects. These defects can capture charges during device operation, resulting in increased SS, pronounced hysteresis, and threshold voltage shift11. It is worth noting that the high crystal quality in single-crystalline KBBF minimizes charge trapping events. The calculated density of states (DOS) for pristine monolayer MoS2 and the KBBF/MoS2 heterostructure (Fig. 3d) demonstrates that KBBF integration on the MoS2 surface is devoid of defect-related gap states within the MoS2 electronic structure. The interface state density (Dit) at the KBBF/MoS2 heterointerface can be calculated from

$${{\mbox{D}}}_{{\mbox{it}}}=\frac{{{\mbox{C}}}_{{\mbox{i}}}}{{\mbox{q}}}\left(\frac{{\mbox{q}}\cdot {\mbox{SS}}}{{\mbox{kT}}{\mathrm{ln}}10}{\mbox{-}}1\right)$$
(1)

where Ci is the capacitance of top-gate dielectrics, q signifies the electron charge, k is the Boltzmann constant and T represents the test temperature. A remarkably low Dit  ≈ 5.5 × 1010 cm−2 eV−1 can be obtained, indicating its advantage over previously reported MoS2 FETs with high-κ gate dielectrics. In addition, since K+ ions are located between the layers, any migration behavior of these ions would also affect the device performance. We calculated the migration energy barriers of K+ ions for both intralayer and interlayer migration. As shown in Supplementary Fig. 16, the maximum intralayer migration energy barrier of K+ ions is 1.1 eV, while the interlayer migration energy barrier for K+ ions passing through the Be2BO3 layer reaches 6.8 eV. These results indicate the absence of ionic migration behavior in KBBF, which is also one of the reasons for its small hysteresis.

These results demonstrate that our devices exhibit excellent performance in terms of SS, on/off ratio, hysteresis, and Dit. To further highlight the advantages of the KBBF dielectric layer, we have also summarized key parameters of state-of-the-art 2D transistors, such as dielectric constant, Ebd, on/off ratio, SS, and hysteresis, as presented in Supplementary Table 1. Furthermore, we also conducted tests on the stability of the device. As shown in Supplementary Fig. 17, our FETs demonstrate excellent air environmental stability over a six-month period, underscoring the durability of the KBBF dielectric layer. Bias temperature instability (BTI) measurements serve as a complementary for evaluating the reliability of transistors. By applying a gate voltage stress of −2 V for different durations to the devices with an EOT of 0.9 nm at 350 K, we characterized the shift in their threshold voltage. It can be seen that although the traps present in the KBBF dielectric may alter the charge state of the devices under negative gate voltage, the threshold voltage of the MoS2 FETs exhibits only a slight variation with gate-biasing time (Fig. 3j). To evaluate the operational stability of the devices, we conducted continuous on/off switching tests. As shown in Supplementary Fig. 18, the devices maintained stable performance over 1000 switching cycles at Vtg = ±2 V and Vds = 50/500 mV. These findings suggest that the transistors with KBBF dielectrics exhibit excellent stability and reliability, which may enable them to play a pivotal role in the development of next-generation 2D devices.

Shorter channel FETs and logic inverter

Although the top-gated FETs with KBBF dielectrics exhibit excellent performance in terms of on/off ratio and SS, the on-state current is still limited by the relatively long channel length and the partial control over the channel semiconductor from the local top gate. Therefore, we fabricated short-channel MoS2 FETs with a back-gate configuration using ultrathin KBBF dielectrics. The FETs with different channel length (40, 80, and 200 nm) were integrated by graphene gate, MoS2 channel and KBBF gate dielectrics. The SEM image of the FET was shown in Supplementary Fig. 19a and the specific preparation process was depicted in Supplementary Fig. 20. The shorter channel MoS2 FETs gated by KBBF dielectrics (EOT = 1.7 nm) exhibit great switching characteristics at different channel lengths (Supplementary Fig. 19b). An excellent on/off ratio of over 1010 and a small SS of 80 mV dec−1 was obtained for the 80 nm short-channel device (Fig. 4b). The corresponding output characteristic curves also confirms the promising on-state current over 400 μA μm−1 due to the reduction in channel length and excellent electrostatic control of the gate insulator (Fig. 4c). With the decrease of the channel length, drain-induced barrier lowering (DIBL) becomes predominant for the device performance12. The use of an ultrathin KBBF insulator allows for better channel control, thereby mitigating the DIBL in short-channel devices, which can be calculated to be as low as 96 mV V−1 for devices with 80 nm channel lengths.

Fig. 4: Short-channel MoS2 FETs and logic inverter based on KBBF dielectric.
Fig. 4: Short-channel MoS2 FETs and logic inverter based on KBBF dielectric.The alternative text for this image may have been generated using AI.
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a Schematic of short-channel MoS2 FET. In this structure, from bottom to top are the Si/SiO2 substrate, graphene gate, KBBF dielectric material, and MoS2 channel. b Transfer characteristic curves of MoS2 FET with channel length of 80 nm. Inset, the AFM image of short-channel MoS2 FET. Scale bar, 500 nm. c Output characteristic curves of 80 nm-channel length MoS2 FET. d The false-coloured SEM image of the logic inverter (NOT gate) consisting of two top-gated MoS2 FETs. Scale bar, 2 μm. Vin, Vout, and Vdd represent the input voltage, output voltage, and supply voltage, respectively. e Voltage transfer characteristic of the inverter. Inset, the equivalent circuit of the inverter. f Voltage gain of the inverter.

To assess the performance of our KBBF dielectrics in functional devices, a logic inverter (NOT gate) was constructed using a top-gated configuration (Fig. 4d and Supplementary Fig. 21). Thanks to the superior gate modulation properties of KBBF/MoS2 FETs, the transfer characteristics of inverter exhibit a rapid state transition within a specific voltage range, resulting in a large voltage gain of approximately 29 at Vdd = 2 V (Fig. 4e, f). It is worth noting that even if the Vdd is reduced to 0.1 V, the inverter retains its ability to perform logical inversion. The combination of high voltage gain and compatibility with low operating voltages makes KBBF-based inverters highly promising for integration into high-density, low-power logic circuits.

Discussion

We have demonstrated that KBBF dielectrics can be prepared from mechanically exfoliation and integrated as a vdW dielectric layer in 2D electronics. The KBBF dielectrics possess a wide bandgap (~8.03 eV), large bulk dielectric constant (~63), low leakage current (10−6 A cm−2) and excellent electrical reliability. Due to the prominent dielectric properties and vdW interface, MoS2 FETs with KBBF gate dielectrics shown an ultimate SS (60 mV dec−1), a high on/off ratio (109), a small hysteresis (9.1 mV on average), and convincing operational stability. In addition, we also demonstrate the potential of KBBF in short-channel devices and logic devices. The progress in ultrathin KBBF development paves the way for manufacturing next-generation 2D transistors with high performance and low-power consumption.

Methods

Growth of crystalline KBBF

The KBBF crystals were synthesized in two steps, mainly following the procedures described in previous references45,46. First, polycrystalline KBBF was prepared via a conventional solid-state reaction according to the following equation:

$$6{{\rm{BeO}}}+3{{\rm{KB}}}{{{\rm{F}}}}_{4}+{{{\rm{B}}}}_{2}{{{\rm{O}}}}_{3}\to {{\rm{K}}}{{{\rm{Be}}}}_{2}{{\rm{B}}}{{{\rm{O}}}}_{3}{{{\rm{F}}}}_{2}+{{{\rm{BF}}}}_{3}\uparrow$$

Stoichiometric amounts of BeO (purity 99.9%), KBF4 (purity 99%), and B2O3 (purity 99.99%) were thoroughly mixed and placed in a platinum crucible. The mixture was heated above 700 °C and maintained at this temperature for 48 h to obtain polycrystalline KBBF. Subsequently, single crystals of KBBF were grown by the flux method using KF-B2O3 as the flux. An appropriate mixture of the KBBF polycrystalline powder and the flux was charged into a platinum crucible, heated to 800 °C, and held for 48 h. The melt was then cooled to 750 °C at a rate of 10 °C h−1, followed by slow cooling to 630 °C at 3 °C day⁻1. Afterward, the temperature was lowered to room temperature within two days. The as-grown KBBF crystals were obtained by dissolving the remaining flux in dilute acid.

Preparation of ultrathin KBBF nanosheets

Thinner KBBF nanosheets were obtained by mechanically exfoliating the bulk crystal using Scotch tape after layer sliding, and then using polydimethylsiloxane (PDMS) as an intermediate carrier and with the help of a transfer platform to transfer it onto the target substrates22. In a typical process, a few KBBF crystals were sandwiched between two pieces of weighing paper and a plastic rod was then rolled gently in one direction on the surface to apply a shear force on the crystals, causing sliding between adjacent layers. A certain amount of the treated KBBF crystals was then cleaved repeatedly using Scotch tape.

Materials characterization

The morphological characterization and thickness measurement of exfoliated KBBF nanosheets were performed by an optical microscope (BX51, Olympus) and AFM (Dimension Icon, Bruker). The XRD (D2 PHASER, Bruker) was carried out to determine the crystal structure of bulk KBBF. HRTEM images were characterized using an aberration-corrected TEM (JEM-ARM200F, JEOL) operated at 200 kV. UPS was obtained from AXIS SUPRA using a helium lamp source emitting.

Dielectric properties measurements

The dielectric properties of KBBF were measured in the metal–insulator–metal device. The bottom electrodes (10/40 nm Cr/Au) were first patterned onto the SiO2/Si substrate by the electron-beam lithography (EBL, ELPHY Plus, Raith GmbH) and electron-beam evaporation (Nexdep, Angstrom Engineering). KBBF nanosheets were then transferred onto the bottom electrode using PDMS on an optical transfer platform. Top electrodes were finally patterned with the same procedure. The current versus voltage curve and capacitance measurements were conducted using a Keithley B1500A semiconductor characterization system.

Computation details

The calculations of bandgap and DOS were conducted using the Vienna Ab initio Simulation Package (VASP)47. The projected augmented wave (PAW) method was employed to describe the ion-electron interactions, with a plane-wave basis set cutoff energy set to 520 eV48. The generalized gradient approximation with the Perdew–Burke–Ernzerhof (PBE) functional was utilized49, along with hybrid functional calculations based on the Heyd-Scuseria-Ernzerhof (HSE06) parameters50,51. Specifically, the HSE06 functional was utilized to yield a precise bandgap value for bulk KBBF. A gamma-centered k-point sampling grid for Brillouin zone integration are generated by VASPKIT with a resolution of 0.0452. The convergence thresholds for total energy and atomic forces were set to 10−5 eV and 2 × 10−2 eV Å−1, respectively. The DFT-D3 dispersion correction method developed by Grimme was included to account for vdW interactions53.

The calculations of dielectric constant and ionic migration were performed using the PAW method, as implemented in the VASP 6.4.3 code54. A plane-wave energy cutoff of 520 eV and the semilocal PBE functional were employed throughout all calculations. The Brillouin zones were sampled using Γ-centered k-meshes with a k-spacing of 0.2 Å−1. The structures were fully relaxed until the total force on each atom was less than 0.01 eV Å−1. The ionic and electronic components of the material’s dielectric constant were acquired via the Density Functional Perturbation Theory approach and the frequency-dependent linear response method, respectively. Specifically, the electronic component of the dielectric constant was calculated using the HSE06 hybrid functional. Additionally, the ionic migration energy barrier was determined using the Climbing Image Nudged Elastic Band method55,56.

Device fabrication and electrical measurements

First, monolayer or few–layer MoS2 flakes were obtained with mechanical exfoliation onto the SiO2/Si substrate. Bi/Au (10/50 nm) electrodes were patterned using EBL followed by deposition of metal. After lift-off of metal in acetone, the KBBF nanosheet was transferred onto the MoS2 channel using PDMS films and a gate electrode was fabricated onto the KBBF nanosheet. The short-channel device was prepared by using few–layer graphene as gate electrodes, and then successively transferring KBBF and MoS2 as the dielectric and channel material. Electrical characterization of the devices was performed using a Keithley 4200 semiconductor parameter analyser. All measurements were carried out under the high vacuum (10−6 torr) condition to reduce the gas adsorption on device surface.