Thermally stable Bi₂Te₃/WSe₂ Van Der Waals contacts for pMOSFETs application

Abstract

Novel van der Waals (vdW) contacts formed by layered Bi₂Te₃ are found effective in improving the performance of WSe₂ pMOSFETs. As compared with conventional transition metal-based Ni/Au S/D contacts, over 10³ times on-state current improvement is achieved. vdW interface formation between Bi₂Te₃ and WSe₂ is confirmed by X-ray diffraction analysis and scanning transmission electron microscope observation. An atomically flat Bi₂Te₃/WSe₂ vdW interface, where the number of defects could be reduced as small as possible, contributes to the suppression of Fermi-level pinning caused by defect-induced gap states. Moreover, the semimetal-like characteristics of Bi₂Te₃ are also effective in minimizing the impact of metal-induced gap states. These features offer WSe₂ pMOSFETs with exceptional S/D junction characteristics, including suppressed off-state leakage and a higher on–off ratio. In addition, it is found that WSe₂ pMOSFETs with Bi₂Te₃ S/D contacts have excellent thermal stability, maintaining device performance even after 400 °C annealing, which is very promising for CMOS back-end-of-line application. The layered tellurides, reconciling low contact resistance and high thermal stability, are promising, particularly from the perspective of their application in the manufacturing process.

Introduction

The device performance of transition metal dichalcogenide (TMDC) metal-oxide-semiconductor field-effect transistors (MOSFETs) has been constrained by a large contact resistance owing to severe Fermi level pinning (FLP) between metal electrodes and TMDCs^1,2,3. The origins of FLP are usually attributed to the metal-induced gap states (MIGS) owing to metal wave function tailing into forbidden energy states⁴ or disorder-induced gap states (DIGS) owing to interfacial disorders/defects at metal/semiconductor interface⁵. For the past few decades, several approaches have been studied on TMDC for both n and pMOSFETs to alleviate FLP. Semimetal bismuth (Bi) has been shown to reduce MIGS because of its small density of states (DOS) near the Fermi level, which is very promising to enhance the device performance of MoS₂ nMOSFETs⁶. However, the thermal stability of Bi is a major concern when considering its application to CMOS fabrication⁷. Besides semimetal material, van der Waals (vdW) contacts were also found effective in enhancing the device performance of MoS₂ nMOSFETs as well as WSe₂ pMOSFETs with metal contacts including In⁸, Au⁹, SnSe₂¹⁰, NiSe¹¹, and a-GeTe¹². In the meantime, the atomically flat vdW interface has a great potential to eliminate the interfacial disorders/defects between the contact material and TMDC, where the DIGS can also be suppressed. Nevertheless, the thermal stability of these kinds of contact materials are still unclear.

Recently, Sb₂Te₃, a famous and well-studied layered phase-change memory material^13,14, has been proven as a promising S/D contact material for MoS₂ nMOSFETs with low contact resistance¹⁵. Through appropriate post-metallization annealing (PMA), the well-aligned vdW Sb₂Te₃/MoS₂ interface can be achieved by the sputtering technique. Besides, Sb₂Te₃ is a degenerate narrow band gap (~ 0.3 eV) semiconductor with p-type conduction, where the Fermi level of Sb₂Te₃ usually resides around the valence band maximum^16,17,18. This feature allows Sb₂Te₃ to possess a semimetal-like characteristics. Meanwhile, since the Fermi level of Sb₂Te₃ is aligned near the conduction band minimum of MoS₂, Sb₂Te₃ can reduce the contact resistance of MoS₂ nMOSFETs by a mechanism of suppressing the FLP and resultant small barrier height for electrons. However, for realizing TMDC CMOS logic devices, not only MoS₂ nMOSFETs but also pMOSFETs should be considered. WSe₂ is a well-known p-type TMDC material, showing high intrinsic hole mobility¹⁹. Although high-performance MoS₂ nMOSFETs with high-quality CVD-grown MoS₂ channels have been generally demonstrated worldwide, the WSe₂ pMOSFETs with comparable performance to the MoS₂ nMOSFETs are still beset with difficulties^20,21,22, owing to unstable monolayer channel quality²³, ambipolar transport behavior²⁴ and large contact resistance²².

Searching for a similar Te-based material but with high electron affinity/work function for WSe₂ pMOSFETs application, we found Bi₂Te₃ is a promising candidate. Bi₂Te₃ shows the similar crystal structure as Sb₂Te₃ with slightly different lattice constants. Nevertheless, Bi₂Te₃ exhibits a tendency to become a degenerate n-type semiconductor, where its Fermi-level locates near the conduction band minimum²⁵. Figure 1 shows the comparison of band alignment of Sb₂Te₃ with MoS₂ and Bi₂Te₃ with WSe₂ as depicted using the theoretical/experimental band parameters^{25,26,27,28,29}. As mentioned and already demonstrated, judging from the band alignment, Sb₂Te₃ is suitable for MoS₂ nMOSFETs, while Bi₂Te₃ has a potential being compatible for WSe₂ pMOSFETs.

Fig. 1

The band alignment of Sb₂Te₃/MoS₂ and Bi₂Te₃/WSe₂, indicating the Te-based contacts are suitable for fabricating MoS₂ nMOSFETs and WSe₂ pMOSFETs. The figure is remodified from Fig. 5a in Ref. 15.

In this work, monolayer (1L) WSe₂ pMOSFETs with Bi₂Te₃ S/D contacts were fabricated and subjected to PMA at different temperatures to verify the feasibility of Bi₂Te₃ as a contact material and to investigate its thermal stability. The Bi₂Te₃/WSe₂ can also form a well-aligned vdW interface under appropriate thermal treatment, just like that of Sb₂Te₃ on MoS₂. It is worth noting that significant device performance enhancement of the WSe₂ pMOSFET with Bi₂Te₃ S/D contacts was observed as compared with the controlled device using the Ni/Au contacts, indicating the possibility of contact resistance reduction at the Bi₂Te₃/WSe₂ interface. Most important of all, the S/D contact characteristics and device performance can maintain or even improve after 400 °C PMA, suggesting the high thermal stability of Bi₂Te₃ and the feasibility of applying it to CMOS fabrication_.

Results and discussion

Figure 2a is the top view of optical microscope (OM) image of CVD-grown WSe₂ flakes, where the WSe₂ flakes consist of WSe₂ with different thickness including 1L, two-layer (2L) and bulk region with layer numbers over 10L. The comparison of Raman spectra of WSe₂ with different thicknesses is shown in Fig. 2b. It is found that the distribution of Raman peaks is very sensitive to WSe₂ thickness and can be used as a fingerprint for WSe₂ with different layer numbers. For WSe₂ with multi-layers over 10L, obvious ${E}_{2g}^{1}$ (248. 1 cm⁻¹) mode and A_1g mode (251.8 cm⁻¹) peaks were observed, which agrees with the spectra extracted from a WSe₂ bulk crystal³⁰. On the other hand, for few-layer WSe₂, the ${E}_{2g}^{1}$ mode and A_1g mode merged or degenerated into a single peak and 2LA(M) mode near 261.2 cm⁻¹ resulting from the second-order Raman mode owing to two-phonon scattering at the M point of the Brillouin zone^31,32 appeared. Besides, as compared with multi-layer WSe₂ (the inset of Fig. 2b), the absence of ${B}_{2g}^{1}$ peak at around 308.5 cm⁻¹ is a signature to confirm the monolayer thickness of the WSe₂ channel^30,33.

Fig. 2

(a) The optical microscope (OM) image of the top view of CVD-grown WSe₂ with different thicknesses. The scale bar is 10 μm. (b) The comparison of Raman spectra of WSe₂ with different thicknesses. The fingerprint of Raman peaks is very sensitive to WSe₂ thickness. The inset shows WSe₂ Raman spectra focusing on Raman shift from 290 to 320 cm⁻¹.

The WSe₂ samples used for X-ray diffraction (XRD) analysis can be separated into two kinds. One mainly consists of 1L WSe₂ with small portion (< 10%) of multi-layer WSe₂, which will be referred to as 1L WSe₂ afterward. The other mainly consists of multi-layer WSe₂ with layer numbers over 10L, which will be referred to as > 10L WSe₂ afterward. Figure 3a,b shows the XRD θ/2θ scan of W/Bi₂Te₃/WSe₂/SiO₂/Si stacked films before and after PMA at temperatures from 200 to 450 °C extracted from 1L WSe₂ and > 10L WSe₂ samples. For the as-deposited sample, a small peak of Bi₂Te₃ 015 can be found at around 2θ = 28°. This is the strongest peak observed for the powder sample³⁴, indicating the as-deposited Bi₂Te₃ film consists of randomly oriented polycrystalline with tiny grain size. The Bragg reflections of the crystalline Bi₂Te₃ (001) plane emerged after 200 °C PMA and became much stronger after 400 °C PMA, indicating that the Bi₂Te₃ crystal grains changed the orientation from random to c-axis oriented through thermal treatment. Note that highly c-axis oriented Bi₂Te₃ and WSe₂ peaks were still present even after 400 °C PMA, suggesting that the layer structure of Bi₂Te₃ film and the well-aligned Bi₂Te₃/WSe₂ interface preserved. This behavior of thermal-induced crystallization of Bi₂Te₃ on WSe₂ is very similar to that of Sb₂Te₃/MoS₂ case¹⁵. However, further annealing at 450 °C resulted in a decrease of the peak intensity for both Bi₂Te₃ and WSe₂ peaks, indicating the degradation of the interfacial quality of the heterostructure. From a materials point of view, the Bi₂Te₃/WSe₂ heterostructure can sustain at least 400 °C annealing, which meets the thermal budget requirement of back-end-of-line (BEOL) for CMOS fabrication. Moreover, the peak intensity of Bi₂Te₃ 006 and 0015 peaks is much stronger for Bi₂Te₃ on 1L WSe₂ (Fig. 3a) as compared with those on > 10L WSe₂ (Fig. 3b), suggesting Bi₂Te₃ has better crystallinity on 1L WSe₂. This phenomenon was also confirmed in the STEM cross-sectional images as shown in Fig. 3c,d for W/Bi₂Te₃ stacked film deposited on 1L WSe₂ and > 10L WSe₂ after 400 °C annealing. For W/Bi₂Te₃ on 1L WSe₂ (Fig. 3c), a well-aligned layered structure of Bi₂Te₃ is clearly observed without any in-plane grain boundaries and distinct defects at this scale. Conversely, a clear grain boundary (yellow dashed line) was observed for those on > 10L WSe₂ (Fig. 3d). It is found that SeO_x on the surface of > 10L WSe₂ hinders the atomic alignment between Bi₂Te₃ and WSe₂. Moreover, some grains do not show c-axis orientation as indicated by absence of lattice fringes parallel to the substrate surface. Since selenium (Se) has very low chemical reactivity and the selenization of WO₃ only happens at certain growth condition, the Se may tend to pile up on > 10L WSe₂ during CVD growth owing to incomplete reaction³⁵. The Se residues will then lead to SeO_x formation after air exposure.

Fig. 3

XRD θ/2θ scan of W/Bi₂Te₃/WSe₂/SiO₂/Si stacked films before and after PMA from 200 to 450 °C extracted from (a) 1L WSe₂ and (b) > 10L WSe₂. The high-resolution scanning transmission electron microscope (STEM) cross-sectional images of 400 °C annealed W/Bi₂Te₃ stacked film as deposited on (c) 1L WSe₂ and (d) > 10L WSe₂. The yellow dashed line indicates the boundary between polycrystalline Bi₂Te₃ with tiny grain size and layered Bi₂Te₃.

A detailed energy dispersive X-ray (EDX) mapping analysis of the Fig. 3d is presented. (see Supplementary Fig. S1). In addition, surface roughness for thick WSe₂ film may affect the growth behavior of Bi₂Te₃ film. This evidence indicates that the surface cleanness as well as flatness of WSe₂ are key factors for transferring poly crystalline Bi₂Te₃ into a highly oriented structure during thermal treatment.

Figure 4a shows the smallest repeating cell of the Bi₂Te₃/WSe₂ vdW interface viewed from the [001] (c-axis) direction based on the lattice information, where Bi₂Te₃ possesses lattice constants of a = b = 4.388 Å and c = 30.46 ų⁶, and those of WSe₂ are a = b = 3.288 Å and c = 12.989 ų⁷. Note that since both materials adopt hexagonal symmetry, the deposited Bi₂Te₃ could follow the atomic alignment of underlayer WSe₂, where the atomic positions of terminated Te and Se nearly match every three and four unit cells, respectively, along the in-plane direction. Moreover, thanks to the layered nature of Bi₂Te₃, the large in-plane lattice mismatch does not influence the growth on WSe₂, which is known as the vdW epitaxy³⁸. Figure 4b shows the High-Angle Annular Dark Field (HAADF)-STEM images focusing on the interface between Bi₂Te₃ and WSe₂, where Bi₂Te₃ is also fabricated by sputtering as mentioned in Fig. 3, and Fig. 4c–f correspond to the EDX mapping analysis of W, Se, Bi, and Te. The heterostructure is subjected to a 400 °C annealing process. Note that as can be seen in Fig. 4c, the elemental mapping of W exhibits two lateral lines, indicating the observed area contains bilayer WSe₂. Nevertheless, the discussion regarding the interfacial stability is still valid for Bi₂Te₃/2L-WSe₂ heterostructure. A vdW interface composed of Bi₂Te₃ quintuple layer (QL) (Te-Bi-Te-Bi-Te stacking) and WSe₂ monolayer (Se-W-Se stacking) is clearly visible. It was found that the Bi₂Te₃ layer contains not only QLs but the bilayer (BL) can be also seen (Fig. 4b).

Fig. 4

(a) A top-view illustration of the smallest repeating cell of the Bi₂Te₃/WSe₂ vdW interface. To prevent complexity, only Te and Se atoms adjacent to a vdW gap are shown. (b) The enlarged HAADF-STEM images of the Bi₂Te₃/WSe₂ interface, indicating the formation of the vdW interface. The EDX mapping of (c) W, (d) Se, (e) Bi, and (f) Te at the Bi₂Te₃/WSe₂ interface, suggesting no chemical interaction occurs.

The same BL stacking fault, known as bilayer swapping, was reported for Sb₂Te₃, but the electrical properties such as carrier concentration are not largely influenced by the presence of BL^39,40. According to the EDX mapping, neither interfacial mixing nor interdiffusion is observed at the Bi₂Te₃/WSe₂ interface, indicating that the vdW interface can be maintained even after 400 °C annealing. We believe that the almost defect-free and highly stable vdW interface could provide the Fermi-level unpinning at the Bi₂Te₃/WSe₂ interface, which helps to enhance the device performance of the WSe₂ device.

Figure 5 shows the typical height and average work function (WF) profile of the Bi₂Te₃/WSe₂ and Ni/WSe₂ interface extracted by Kelvin Probe Force Microscopy (KPFM), respectively. Since the electrodes on WSe₂ were fabricated through lift-off process, the abrupt edge between electrodes and WSe₂ is hard to obtain owing to the photoresist residue. We define the averaged CPD of WSe₂ away from the interface about 1 μm. The averaged WF value of WSe₂ of 5.37 eV was derived through the CPD difference from Au (5.47 eV)⁴¹ reference pad on WSe₂. The corresponding optical images and KPFM CPD images are also presented (see Supplementary Fig. S2). The WF of Bi₂Te₃ and Ni were then determined to be 5.21 and 5.02 eV, respectively. The obtained WF value of WSe₂ and Bi₂Te₃ are all very close to the theoretical value as depicted in Fig. 1. Moreover, a lower Fermi-level difference is expected for Bi₂Te₃/WSe₂ than that of Ni on WSe₂. If the Fermi-level is unpinned, Bi₂Te₃ has a great potential to achieve better p-type transport properties on WSe₂.

Fig. 5

Height profile and corresponding averaged work function profile of the (a) Bi₂Te₃/WSe₂ and (b) Ni/WSe₂ interface.

To investigate the electrical properties of Bi₂Te₃ on WSe₂ as a contact material, we fabricated the back gate 1L WSe₂ pMOSFETs with Bi₂Te₃ contact. Figure 6a is the detailed process flow and a schematic cross-sectional figure of a 1L WSe₂ pMOSFET with Bi₂Te₃ S/D contacts. Figure 6b shows the Raman spectrum obtained from the channel region between the S/D metal pads of WSe₂ pMOSFET, as shown in the inset, where the electrode gap size is around 5 μm. The peak position shift between ${E}_{2g}^{1}$ mode and A_1g mode and the absence of ${B}_{2g}^{1}$ peak is in good agreement with 1L WSe₂, as mentioned in Fig. 2.

Fig. 6

(a) The detailed process flow and a schematic cross-sectional figure of a 1L WSe₂ pMOSFET with Bi₂Te₃ contacts and Au back-gate. (b) 1L WSe₂ Raman spectrum obtained from the channel region between the S/D metal pads. The inset shows the OM image of a top view of the back-gate 1L WSe₂ pMOSFET.

Figure 7a compares the I_D–V_G transfer curves extracted from the 1L WSe₂ pMOSFETs with Bi₂Te₃ and Ni/Au S/D contacts. For a fair comparison, all the devices were subjected to PMA at 200 °C for 10 min. The 5-µm-gate-length WSe₂ pMOSFETs with Bi₂Te₃/W contacts exhibited significant device performance enhancement as compared with those of Ni/Au control devices. A high on–off ratio of ∼10⁶ was obtained at a V_D of -50 mV. Moreover, the on-state current (I_on) of the devices with Bi₂Te₃/W contacts considerably increases to approximately 10³ times greater than that of the MOSFETs using Ni/Au for S/D contacts. These results suggest a significant contact resistance reduction by employing Bi₂Te₃ contacts, which can be attributed to the low Fermi-level difference between Bi₂Te₃ and WSe₂ (Fig. 5). Due to the semi-metallic characteristics of Bi₂Te₃ for suppressing MIGS and vdW interface for suppressing DIGS, the Fermi-level between Bi₂Te₃ and WSe₂ tends to unpin, so the small Fermi-level difference can be maintained and leads to better device performance. Besides Ni/Au S/D contacts, we also compare Bi₂Te₃ contacts with Cr/Au contact (see Supplementary Fig. S3). Significant device performance enhancement was also observed, suggesting the effectiveness of Bi₂Te₃ contacts for improving junction characteristics on WSe₂. The thermal stability of 1L WSe₂ pMOSFETs was also investigated. Figure 7b shows the comparison of I_D-V_G transfer curves at V_D of -50 mV and -2 V for 1L WSe₂ pMOSFETs with Bi₂Te₃/W contacts before and after the PMA process at different temperatures. Reduced off-state leakage (I_off) and enlarged on–off ratio with increasing PMA temperature are visible, indicating the S/D junction characteristics improvement through thermal treatment. At V_D of − 2 V, increasing I_on is observed with increasing PMA temperature, which is more obvious in the linear scale as shown in Fig. 7c. This indicates the contact resistance reduction and the high thermal stability of Bi₂Te₃/WSe₂ contacts. Approximately 3 times I_on enhancement was achieved after 400 °C PMA as compared with its as-deposited counterpart, suggesting the benefits of vdW interface formation for reducing contact resistance. The I_on enhancement mainly resulted from the contact resistance reduction instead of gate leakage current (I_G), as I_G remains considerably low during the thermal treatment, as shown in the Fig. 7d.

Fig. 7

(a) Comparison of I_D-V_G transfer curves of devices with Bi₂Te₃/W and Ni/Au S/D contacts on 285-nm-thick SiO₂ dielectrics. (b) Comparison of I_D-V_G transfer curves of devices with Bi₂Te₃/W contacts before and after the PMA process at different temperatures. (c) The linear scale of I_D-V_G transfer curves shown in Fig. 6b. (d) The comparison of I_G of devices with Bi₂Te₃/W contacts before and after the PMA process at different temperatures.

Nevertheless, kinks at the subthreshold region were visible after thermal treatment and got worse at 400 °C. Since the WSe₂ of our devices is not covered by any protection layer, this phenomenon may be attributed to the interfacial degradation between WSe₂ and backside SiO₂ and the damage of WSe₂ itself_.

Conclusion

Thermally stable Bi₂Te₃/WSe₂ vdW contact up to 400 °C was fabricated, and significant device performance improvement was realized owing to the atomic-level defect-free vdW interface. The Bi₂Te₃/WSe₂ heterostructure can go through and maintain its quality at least after 400 °C annealing, which fulfills the requirement for the BEOL CMOS process. Moreover, significant enhancement of device performance in terms of up to 10³ times current improvement was demonstrated using Bi₂Te₃/WSe₂ contacts as compared with conventional transition metal contacts. This also indicates significant contact resistance reduction. All evidence shown in this work supports that layered tellurides can be applied to not only MoS₂ nMOSFETs but also WSe₂ pMOSFETs as S/D contacts, which is very promising for TMDC CMOS applications.

Methods

Synthesis of WSe₂

By using chemical vapor deposition (CVD), WSe₂ flakes were deposited on SiO₂ (285 nm)/Si substrates at 880 °C with WO₃ powder, Se beads, and KBr powder^42,43. KBr powder was used as the growth promoter⁴⁴.

Bi₂Te₃ deposition by sputtering

To investigate the crystal quality of Bi₂Te₃ on WSe₂ and its applicability to contact material, 20-nm-thick Bi₂Te₃ and 30-nm-thick tungsten (W) films were deposited onto the WSe₂ by magnetron sputtering at room temperature (300 K) (QAM-4, ULVAC KYUSYU Corp.)^14,45. W was treated as a protection layer for Bi₂Te₃ during the thermal treatment.

Material characterization

Raman analysis was used to determine the thickness of the WSe₂ layer. The Raman spectra were extracted from the HORIBA LabRAM Raman spectrometer with 488 nm wavelength laser excitation using a power of 5 mW. X-ray diffraction (XRD) and scanning transmission electron microscope (STEM) were used to investigate the crystallinity of Bi₂Te₃ and the Bi₂Te₃/WSe₂ interface. For XRD analysis, Cu-Ka (l = 1.542 Å) was used in a Bragg–Brentano geometry (Ultima IV, Rigaku Corp.). A focused ion beam (FIB) technique was used to prepare the STEM sample, and JEM-ARM200F (JEOL, Ltd.) was used to study the cross-sectional images of Bi₂Te₃ and WSe₂ and energy dispersive X-ray (EDX) mapping with an accelerating voltage of 200 kV was performed. Kelvin probe force microscopy (KPFM) was used to measure the contact potential difference (CPD), which can be used to extract the work function difference between metal electrodes and WSe₂. A standard atomic force microscope (Park Systems NX10) was utilized with a conductive cantilever (Olympus AC240TM, Pt coat) for CPD measurement under ambient condition.

Fabrication of back gate 1L WSe₂ MOSFETs

After WSe₂ growth, photolithography was used for defining S/D regions. 20-nm-thick Bi₂Te₃ and 30-nm-thick W films were then deposited onto the WSe₂ layer by magnetron sputtering. The S/D contacts were then fabricated through a lift-off process using acetone and isopropanol (IPA) at 25 °C. Subsequently, the backside SiO₂ of the samples was removed using hydrogen fluoride (HF) solution, followed by back-gate Au deposition using sputtering. Post metallization annealing (PMA) was performed in Ar ambient for 10 min at 200, 300 and 400 °C. The back-gate devices with Ni (50 nm)/Au (50 nm) S/D metal contacts were also fabricated for comparison. Ni and Au were deposited by e-beam evaporator, respectively. To eliminate the impact from WSe₂ quality and WSe₂/SiO₂ interfacial condition on device performance, we fabricated the devices with different S/D metal contacts on the same WSe₂ sample grown by CVD.

Electrical characterization

All electrical characterization of WSe₂ MOSFETs was performed in a standard probe station under atmospheric condition at room temperature, and Keysight B1500A was used for electrical measurements.