Introduction

Research background and motivation

The chips used in advanced graphics processing units (GPUs) integrate billions of transistors and are currently supporting the most powerful GPUs on the market. The excellent performance of advanced GPU chips is achieved by adopting CoWoS-L packaging technology to provide efficient interconnections between the chips. However, the advanced complexity of CoWoS-L packaging technology inevitably pose challenges for FCBGA substrate warpage.

In current FCBGA substrates, the use of BT core boards with build-up films (XY-CTE: 30–60 ppm/°C) to form copper traces leads to increased CTE mismatch effects during thermal expansion and contraction, especially for 600 × 600 mm substrates. This significantly amplifies the mechanical stress on the 20 μm line width due to a sharp increase in the tensile strength of the copper lines, thereby increasing the risk of open-circuit failure. Hence, warpage of the FCBGA substrate not only affects the packaging yield of chips but also adversely impacts their electrical performance.

The reliability of GPU chips, as the core computing power sources of modern autonomous vehicles and AI robots, directly affects system safety. For example, between 2016 and 2020, multiple incidents involving autonomous vehicle autopilot systems misidentifying road conditions or obstacles (such as white trucks or stationary fire trucks) resulted in collisions. Investigations revealed that some cases were linked to transient computational errors in hardware systems (including GPU/FSD chips). An academic study from 2021 on GPU vulnerabilities and robotic safety by a University of Michigan research team demonstrated that by inducing hardware faults in GPUs (e.g., voltage glitches), they could successfully manipulate robots into performing dangerous actions (such as aggressive gripping). The study highlighted that GPU computational errors could bypass software-based fault tolerance mechanisms, necessitating hardware-level safeguards.

In addition to high-end GPU chips, LSI (large-scale integration) chips, such as ASIC and CPU chips, also require extremely complex packaging technology. FCBGA substrate warpage has therefore become an urgent issue that must be resolved.

Key technologies overview

Advanced GPU chips

GPU chips are equipped with strong computing capabilities and are suitable for high-performance computing, data centres and other fields. The adoption of advanced architecture designs results in efficient parallel computing and data processing capabilities. GPU chips are now widely used in gaming, virtual reality, and artificial intelligence.

CoWoS-L packaging technology

CoWoS-L (chip on a wafer on a substrate with a local silicon interconnect and RDL interposer) is an advanced packaging technology primarily used for manufacturing high-performance computing (HPC) and AI components. This technology is a new architecture in the CoWoS (chip on wafer on substrate) series.

FCBGA substrate and CoWoS-L packaging

The FCBGA (flip chip ball grid array) substrate is the raw material for chip packaging, whereas CoWoS-L advanced packaging technology requires the use of the FCBGA substrate.

FCBGA substrate warping

The FCBGA substrate is a high-density semiconductor packaging substrate that can achieve high-speed and multifunctional large-scale integration (LSI). Flip chip technology is used to directly connect chips to the substrate, forming a ball grid array, thereby achieving high-density electrical connections. The FCBGA substrate is characterized by multiple layers, a large area, a high circuit density, a small line width and spacing, and small through-hole and blind hole diameters, making processing difficult.

FCBGA substrate warping refers to the deformation of the substrate during heating and cooling due to a mismatch in the coefficient of thermal expansion (CTE) of the material during the packaging process. This deformation usually manifests as bending or twisting of the substrate surface. The substrate normally comprises different materials that have different thermal expansion coefficients. When the working temperature varies, the stress distribution inside the substrate becomes heterogeneous, and warping occurs as a result. Moreover, multiple heating and cooling cycles during the assembly process of the chips and FCBGA substrates can lead to stress accumulation between materials. This, in turn, can cause warping and ultimately result in chip failure.

FCBGA substrate warpage impact on chips

The impact of FCBGA substrate warpage on chips is generally manifested as follows.

  1. A.

    Stress concentration and cracking: Warping results from a mismatch in the CTE of materials such as silicon chips, packaging compounds, copper, polyimide, etc. This mismatch can cause uneven stress distributions during assembly and packaging, which may lead to chip cracking (or delamination) and failure.

  2. B.

    Reliability issue: Warping may cause chips to crack or delaminate under heavy load usage on site. This is especially true for heterogeneous designs in which chips made of different materials or from different processes are susceptible to warpage impacts in specific areas of asymmetric packaging.

  3. C.

    Performance degradation: Warping can negatively impact the performance of chips, especially in high-performance computing, 5G communication, AI and other fields.

Grace T.H.W. group, history, and material overview

  1. A.

    Grace T.H.W. Group:

    Professor Winston Wong has positioned the Grace T.H.W. Group as a technology-driven enterprise, emphasizing R&D and high-quality manufacture.

    Filling Domestic Technology Gaps in China: Epoxy Base Electronic Material Co., Ltd. (a subsidiary of the Grace T.H.W. Group), was China’s first listed company specializing in electronic-grade epoxy resin production. Its products are widely used in CCLs (copper clad laminates), LEDs, capacitors, and other products, significantly reducing reliance on imported materials.

    Technological Leadership: Grace Fabric Technology Co., Ltd. (a subsidiary of Grace T.H.W. Group), developed ultrathin glass fibre cloth (thickness: 5 μm; 1/10 that of a human hair), establishing globally leading standards. This material is adopted in high-end electronics, such as Sony gaming console motherboards and iPhones.

    Vertical Supply Chain Integration: By consolidating upstream and downstream components (epoxy resin, glass fibre cloth, CCLs, etc.), the Grace T.H.W. Group established a complete electronic materials ecosystem, enhancing China’s domestic supply chain autonomy.

  1. B.

    GBF (Grace Build-up Film):

    Developed by Epoxy Base Electronic Material Co., Ltd., GBF (Grace build-up film) is an advanced semiconductor packaging material, primarily used in advanced packaging, e.g. WLP (wafer-level packaging) and chip substrates.

  1. C.

    GA-688N/GA-688Q Laminates:

    The GA-688N and GA-688Q series are high-end CCLs that were developed by Wuxi Grace Electron Technology Co., Ltd., a subsidiary of Epoxy Base Electronic Material Co., Ltd., for high-frequency and high-speed applications (e.g., 5G and AI servers).

  1. D.

    Low-Dk/Low-CTE Glass & Quartz Fabrics:

    Low-Dk/low-CTE glass fabrics and quartz fabrics are produced by Grace Fabric Technology Co., Ltd. (a subsidiary of the Grace T.H.W. Group), setting benchmarks for China’s high-end electronic materials and demonstrating strong competitiveness for use in AI servers and consumer electronics through promoting technological breakthroughs and supply chain integration.

Chip failure mechanism

The large-scale and high-density packaging of ASICs is usually achieved through the FCBGA, which has a complex structure (as shown in Fig. 1) and comprises materials that can lead to reliability issues (such as fracture failure) when thermal mechanical stress dominates. Fracture failure is caused mainly by stress concentrations, leading to structural fragility. We can track the cracks in the substrate layer by grinding the chip and substrate, as shown in Fig. 2, as noted in reference1. Of particular note is the description in reference1 regarding the fracture of solder joints in the heat affected zone. Accelerated temperature cycling reliability testing was conducted on 90 nm/8-level copper based FCBGA packaged chips, and open circuit failure dominated by thermal mechanical stress was observed when exposed to temperature environment. The crack is located below the UBM, and the dielectric and metal layers are pulled up. All ten dielectric failures occur at the edge of the chip, not at the center. Fracture failure is caused by two main factors: stress concentration and structural fragility. The layering position indicates that the first principal stress is concentrated at the corners or edges of the chip, and the structurally fragile pores in the dielectric are the cause of chip failure. Track cracks in substrate layering by grinding chips and substrates. The open circuit failure is located at the bottom of the second or third layer of the stacked via.

Fig. 1
figure 1

FCBGA packaging structure.

Full size image
Fig. 2
figure 2

Cracks in the through holes of the stacked build-up film.

Full size image

CTE among the chip, FCBGA substrate, and PCB

Warpage is mainly the result of strain caused by the mismatch in the CTE between silicon chips and organic packaging materials (including substrates). The assembly was evaluated for performance reliability through thermal cycling testing (TCT) for up to 1000 cycles in the range from − 55 °C/15 min to 125 °C/15 min. As shown in Fig. 3, a resistance exceeding 1.0 M Ω is caused by solder fracture, according to reference2.

Fig. 3
figure 3

A welding point fracture.

Full size image

FCBGA substrate warpage analysis

Two-layer wiring thin packaging substrates are easily affected by material and structural design imbalances, resulting in excessive warpage. The thinned substrate is prone to bending and warping. The warping of the substrate beyond a certain limit affects the yield and reliability of the chip and substrate mounting. The finite element method can be used to simulate the process of substrate warping, as described in reference3.

FCBGA substrate warpage improvement

FCBGA substrate packaging refers to the chip facing downwards towards the packaging substrate and using metal balls to achieve a connection. However, the use of many metal balls requires a very flat packaging substrate, which may result in a high degree of warpage for the packaging substrate. Packaging substrates are generally composed of resin, fillers, copper foil and solder masks, and the CTEs of these materials are quite different. When these materials are in an environment with large temperature changes, the different CTEs lead to an increased thermal stress, resulting in warpage or deformation of the packaging substrate. Warpage hinders the subsequent packaging substrate development and production. This may also cause the product to warp too much and become unable to be mounted, resulting in product failure. By using numerical simulation software, the possible warpage deformation problems that may occur during the packaging process can be identified, and the locations and root causes of warpage can be determined. On the basis of the warpage modelling results, targeted improvements can be made to the packaging substrate, saving time, reducing costs and yielding significantly improved packaging substrates, according to reference4.

Production of low-CTE build-up film

The current CTEs of the build-up films used in FCBGA packaging substrates are high, and the thermal expansion of the resin in the build-up film is often extensive and can easily cause the substrate to warp. Moreover, external thermal loads can cause dimensional changes in materials due to thermal expansion, as well as changes in the creep rate; such issues include CTE mismatch, which can lead to local stress and ultimately result in packaging structure failure. Functionalized silica has been introduced as a modified filler in the build-up film. Through the reaction between the modified filler and specific functional groups in the resin system, an interconnected network structure can be constructed to restrict the movement of the polymer segments in the build-up film. This helps mitigate the thermal expansion phenomenon, reduce the CTE of the built-up film, and avoid substrate warping and packaging structure failure caused by CTE mismatch, as described in reference5.

The thermal expansion phenomenon of the existing build-up film is obvious and can easily cause significant deformation of the film after curing. Furthermore, a low glass transition temperature leads to poor heat resistance and affects processing performance; at the same time, poor dielectric performance can easily result in significant dielectric losses in high-frequency and high-speed application scenarios, thereby affecting the use of build-up adhesive films. Therefore, by modifying the resin and redesigning the formula, the CTE of the build-up film can be reduced, the high-temperature resistance of the film can be improved, the warpage of the substrate can be reduced, and the safety and reliability of product application can be ensured. Notably, the dielectric constant and dielectric loss are simultaneously reduced, thereby improving the signal transmission speed and efficiency, as described in reference6.

Research methods

Research architecture

The proposed architecture (as shown in Fig. 4) is used to reduce FCBGA substrate warpage by improving the CTE compatibility among the build-up film, core board, and copper foil. This method can be used to improve packaging technologies, such as CoWoS-L packaging technology, and the reliability of LSI chips (large-scale integrated chips), such as ASIC, CPU, and high-end GPU chips. Furthermore, a CTE control technique for FCBGA substrate materials is presented. This CTE control technology not only reduces the warpage of FCBGA substrates and improves the reliability of ASIC, CPU and advanced GPU chips but also maintains ultralow loss for FCBGA substrates, thereby improving the speed and integrity of signal transmission.

Fig. 4
figure 4

Research architecture for improving chip reliability.

Full size image

Research hypothesis

In this study, the following research concepts are explored by analysing and studying chip failure mechanisms1; the CTE relationship among chips, FCBGA substrates, and PCBs2; FCBGA substrate warpage3; FCBGA substrate warpage improvement4; and low-CTE build-up film production5,6 . To increase the reliability and yield of large-scale integrated chips (LSIs), such as GPU, ASIC, and CPU chips packaged in CoWoS-L, it is necessary to minimize the warpage of FCBGA substrates. Therefore, this study experimentally demonstrates that improving the CTE matching between the build-up film and the copper foil can reduce the warpage of the FCBGA substrate. In other words, by controlling the composition of the build-up film, the CTEs of the build-up film and the copper foil can be closely matched, thereby increasing the reliability of GPU, ASIC, and CPU chips.

It is noteworthy in reference5 that the results of the fabrication of the Build-Up film, the CTE of the overlay film, and the warpage test are helpful for the inference of this paper.

Preparation of build-up film

The raw materials for the build-up film used in FCBGA packaging substrates with low thermal expansion coefficient include bisphenol A-type epoxy resin, biphenyl type epoxy resin, biphenyl aromatic alkyl type epoxy resin, phenoxide resin, active ester curing agent, carbodiimide curing agent, phenol curing agent, 4-dimethylaminopyridine, aminated silica, carboxylated silica, and cyclohexanone.

The preparation method of build-up film for FCBGA packaging substrate with low thermal expansion coefficient is as follows: Mix the various raw material components of the low thermal expansion coefficient FCBGA packaging substrate with the build-up film evenly, coat it on a PET release film, dry it at 80 °C for 10 min, remove the PET release film, and obtain a low thermal expansion coefficient FCBGA packaging substrate build-up film with a thickness of 100 μm.

Thermal expansion coefficient test

Cure the FCBGA packaging substrate with PET release film using a build-up film at 100 °C for 30 min, then cure at 190 °C for 90 min, and peel off the release film to obtain the test sample. Cut the test sample into test pieces with a width of about 3 mm and a length of about 20 mm. Use a thermal mechanical analysis device to perform thermal mechanical analysis under the conditions of a preloading force of 0.02N, a temperature range of 25 °C to 260 °C, and a heating rate of 10 °C/min. Perform two heating cycles to obtain the thermal expansion coefficient in the range of 25–150 °C in the second heating curve.

Warping height test

Cut the FCBGA packaging substrate with PET release film into 300 × 300 mm samples using a build-up film, and then press them onto a copper foil with a thickness of 35 μm using a vacuum laminating machine. First, cure at 100 °C for 30 min, then cure at 190 °C for 90 min. After cooling to room temperature, place it horizontally on a flat marble table and observe the highest warpage value in mm. The test results are shown in Table 1. Thermal Expansion Coefficient and Warping Height.

Table 1 Thermal expansion coefficient and warping height.
Full size table

Experiments and results

Inference

As inferred from the literature, the CTE of the build-up film in the FCBGA packaging substrate can be very high, and substrate warpage may easily occur. External thermal loads can cause material size changes due to thermal expansion, resulting in CTE mismatch and local stress, ultimately leading to packaging structure failure. In this research, experimental methods and data from the literature5 were used in analyses, and the results indicated that when the CTE of the build-up film is close to the CTE of copper, the warpage of the FCBGA substrate can be reduced by 92%. This approach differs from that used in current FCBGA substrate and stacking material design, which focuses primarily on matching the chip’s XY-CTE of 5 ppm/°C. In current FCBGA substrates, the use of BT core build-up films (XY‒CTE: 30‒60 ppm/°C) for copper trace formation leads to exacerbated CTE mismatch effects during thermal cycling, especially in 600 × 600 mm substrates. This mismatch intensifies the mechanical stress on the fine-pitch 20 μm line width copper traces, substantially increasing the risk of open-circuit failure.

Influence of packaging materials with different CTEs on substrate warpage:

  1. A.

    When the CTE of the FCBGA substrate build-up film decreases from 39 to 19 ppm/°C or when the CTE of the build-up film is extremely close to the CTE of the copper foil (18 ppm/°C), the degree of substrate warpage can be reduced by up to 92%.

  2. B.

    In addition to controlling the CTE of the FCBGA substrate build-up film, warpage can be reduced by controlling the CTE of the FCBGA substrate core board, which consists of copper foil, resin, and glass fabric.

  3. C.

    Controlling the CTE of the core board and the build-up film for FCBGA substrate is a simple and effective solution for reducing the warpage of high-end multilayer FCBGA packaging substrates.

FCBGA core board CTE control technology

Warpage uncertainty

The warpage of FCBGA packaging substrate results from unevenly distributed stress caused by the CTE mismatch among the copper lines, insulation resin and core boards. Consequently, a change in the shape of the substrate can occur. Few studies have focused on the warpage of FCBGA substrates before packaging.

Effects of the resin, glass fabric type, filler, and plate on the CTE

The above experimental results indicate that the closer the CTE of the build-up film is to that of the copper foil, the lower the degree of warping. Therefore, via collaboration with the R&D centre of the Grace T.H.W. Group, the relationships among copper foil, resin, glass fabric and core board CTEs were explored from the perspective of core board CTE control technology (the FCBGA structure is as shown in Fig. 5).

Fig. 5
figure 5

The core board and build-up film in the FCBGA structure.

Full size image
RC (resin content) effects on the stack-designed core board

During the production process of FCBGA substrate core board, resin is used to bond the copper foil and glass fabric together. After heating and expansion, the CTE of the resin is normally the highest, the CTE of the glass fabric is the smallest, and the resin that bonds the glass fabric is restricted. The resin between the copper foil and glass fabric undergoes maximum thermal expansion, resulting in thermal expansion mismatch and internal stress in the board, causing deformation of the plate. The CTEs of the copper foil, glass fabric, and resin are shown in Table 2. In this study, a stacked design with different resin contents (as shown in Table 3) was used to investigate the effects on the expansion and contraction of the core board.

Table 2 CTEs of copper foil, glass fabric, and resin in the core board.
Full size table
Table 3 Core board with a low resin content and stacked structure.
Full size table

It is necessary to further explain the differences between the original stacking structure and the new stacking structure, which will help to understand the influence of resin content on the amount of expansion and contraction. For example, in Table 3, the differences between the original stacking structure 1086RC610 × 1 and the new stacking structure 2112RC520 × 1 for the core board thickness of 0.08 mm are as follows:

  1. 1.

    The content of the laminated resin in the new stacking structure is low, and the curing shrinkage of the resin is small, that is, the expansion and contraction are small.

  2. 2.

    The resin shrinks less and is less likely to cause strong pulling and warping of the core board.

  3. 3.

    Definition of the original and new stacking structures.

Original stacking structure: 1086RC610 (thickness approximately 0.08 mm)

Structure: One 1086 core board and two RC610 semi-cured sheets are laminated together.

Characteristics:

Thin core board (1086): The main body of the structure is a relatively thin core board.

Thicker half cured film (RC610): Use a thicker half cured film to fill and achieve the target thickness.

High resin content: RC610 has a high resin content and good flowability, but the curing shrinkage is also relatively large.

New stacking structure: 2112RC520 (thickness approximately 0.08 mm)

Structure: One 2112 core board and two RC520 semi-cured sheets are laminated together.

Characteristics:

Thicker core board (2112): The main body of the structure is a thicker and more stable core board.

Thinner half cured film (RC520): Use a thinner half cured film, mainly for bonding rather than filling thickness.

Low resin content: RC520 has a lower resin content, better dimensional stability, and smaller curing shrinkage.

When the thickness of the core board is 0.05 mm (excluding the copper foil) and a new stacked structure is considered, the average magnitude of longitudinal expansion and contraction decreases by 339 ppm, and the average magnitude of latitudinal expansion and contraction decreases by 323 ppm. Both values indicate significant reductions in expansion and contraction when the new stacked structure is adopted compared to when the original stacked structure is used, as shown in Table 4.

Table 4 Differences in expansion and contraction of the 0.05-mm-thick core board (excluding copper foil).
Full size table

When the thickness of the core board is 0.06 mm (excluding copper foil) and a new stacked structure is used, the average magnitude of longitudinal expansion and contraction decreases by 181 ppm, and the average magnitude of latitudinal expansion and contraction decreases by 201 ppm. Both values indicate notably reduced expansion and contraction when a new stacked structure is adopted compared to when the original stacked structure is used, as shown in Table 5.

Table 5 Differences in expansion and contraction of the 0.06-mm-thick core board (excluding copper foil).
Full size table

When the thickness of the core board is 0.08 mm (excluding copper foil) and a new stacked structure is adopted, the average magnitude of longitudinal expansion and contraction decreases by 4 ppm, and the average magnitude of latitudinal expansion and contraction decreases by 145 ppm. Both values demonstrate reduced expansion and contraction when the new stacked structure is adopted compared to when the original stacked structure is used, as shown in Table 6.

Table 6 Differences in expansion and contraction of the 0.08-mm-thick core board (excluding copper foil).
Full size table

The above experimental results demonstrate that changing the RC of the stacked structure can affect the expansion and contraction of the core board, which may lead to warpage. After reducing the RC in the core board, the overall shrinkage is approximately 200 ppm less than it was originally. These results are promising for reducing the warpage of the core board.

Glass fabric types on Z-CTE of the stack-designed core board

The core board with a stacked design used in this experiment is described in Table 7, and GA-HF-PF7 material; glass fabric types of 7628, 2116, 1080, and 106; and a plate thickness (H/H oz copper foil) of 1.00 mm are used. The test results are shown in Table 8.

Table 7 PF7 plates constructed by stacking different types of glass fabric.
Full size table
Table 8 Properties of PF7 plates constructed with different types of stacked glass fabric.
Full size table

The experimental results indicate that as the weight of the glass fabric decreases, the resin content increases. As a result, the Z-CTE of the core board increases, as shown in Table 8.

Filler ratios on Z-CTE of the stack-designed core board

The material system used in this experiment is GA-LD-HF, with filler addition ratios (mass percentages) of 40, 50, 60, 65, and 70. The core plate thickness (1/1 oz copper foil) is 1.50 mm, and the stacking structure is 7628RC57.0 × 6. The test results are shown in Table 9.

Table 9 Effects of different filler ratios on the Z-CTE and warpage of core boards.
Full size table

The results of this experiment indicate that as the filler ratio increases from 40 to 70%, the warping height of the core board decreases from 0.94 to 0.02 mm.

Influence of different plates in the core board on XY-CTE

The performance of GA-688 and GA-686 (both produced by WGET) plates used as core boards was compared, and the results showed that the XY-CTE of the GA-688 plate was superior to that of the GA-686 plate. The GA-688 plate exhibits both low warpage and ultralow loss characteristics, as shown in Table 10 and Figs. 6, 7 and 8.

Table 10 XY-CTE results for the GA-686 and GA-688 plates.
Full size table
Fig. 6
figure 6

XY-CTE comparison for the GA-686 and GA-688 plates.

Full size image
Fig. 7
figure 7

GA-686 plate XY-CTE test.

Full size image
Fig. 8
figure 8

GA-688 plate XY-CTE test.

Full size image

The analysed sample in Fig. 7 is a GA-686 plate, and TMA was heated from 30 to 260 °C at a rate of 10 °C/min for XY-CTE testing.

The analysed sample in Fig. 8 is a GA-688 plate, and TMA was heated from 30 to 260 °C at a rate of 10 °C/min for XY-CTE testing.

CTE control technology

Various CTE control techniques for FCBGA substrate core boards are proposed, such as adjusting the resin content, glass fabric type, filler ratio, and board material to control the CTE of the core board in FCBGA substrates. The control techniques are as follows.

  1. A.

    Changing the resin content (RC) in the stacked structure can affect the expansion and contraction of the core board and may result in warpage. Since resin possesses a relatively high CTE, reducing the RC in the core board with a stacked structure helps reduce the overall shrinkage by approximately 200 ppm compared with that of the original RC. This greatly helps reduce core board warpage.

  2. B.

    Varying the type of glass fabric used, such as by choosing a light-weight glass cloth while increasing the relative RC, can aid in increasing the Z-CTE of the core board.

  3. C.

    As the filler ratio increases from 40 to 70%, the warping height of the core board decreases from 0.94 to 0.02 mm.

  4. D.

    The use of ultra-low-loss board material can result in both low warpage and low insertion loss.

Reduce FCBGA substrate warpage and insertion loss

The key materials in the FCBGA substrate, provided by the R&D centre of the Grace T.H.W. Group, include low-CTE, ultra-low-loss build-up film from the GBF series (XY-CTE is 17–22 ppm/°C, provided by Epoxy Base Electronic Material Co., Ltd., a subsidiary of Grace T.H.W. Group) and ultra-low-loss plates GA-688N and GA-688Q (Df < 0.002, provided by Wuxi Grace Electron Technology Co., Ltd., a subsidiary of Epoxy Base Electronic Material Co., Ltd.). These key materials reduce the warpage and maintain ultra-low losses for the FCBGA substrate, thereby improving the signal transmission speed and integrity of the chip. In particular, GA-688Q, GA-688U, and GA-688N from Wuxi Grace Electron Technology Co., Ltd., can be applied to create ultralow-loss 224G switch backboards and high-speed wafer probe cards. The specifications of the high-frequency high-speed plate products are shown in Table 11. The resin, glass fiber, and copper foil in the SEM images in Table 11 are clearly shown in Fig. 9.

Table 11 High-frequency high-speed plate models.
Full size table
Fig. 9
figure 9

Resin, fiberglass, and copper foil labeling diagram.

Full size image

Below lists the fundamental steps in the production process for copper-clad laminate samples for reference:

  1. 1.

    Raw Material Preparation: Specialty Resins/Glass Fabric

  2. 2.

    Resin Mixing & Treating: Creates Prepreg

  3. 3.

    Copper Foil Treatment: Low-profile/RTF Foil

  4. 4.

    Lay-up & Lamination: High-Temp/High-Pressure Cure

  5. 5.

    Post-Processing & Inspection: Stabilization & Electrical Test

Furthermore, the ultra-low-loss GBF products (provided by Epoxy Base Electronic Material Co., Ltd.) can be used as build-up films for FCBGA substrates. The CTE of these products is controlled in the range of 17–22 ppm/°C, which helps improve the CTE matching between the build-up film and copper, thereby reducing the risk of chip failure. The characteristics of the GBF build-up film products are shown in Table 12.

Table 12 GBF build-up film models.
Full size table

Conclusions

  1. (1)

    When the CTE of the build-up film of FCBGA packaging substrate is too high, the external thermal load can cause local stress in the material due to CTE mismatch, resulting in substrate warpage and ultimately leading to packaging structure failures for ASIC, CPU, and high-end GPU chips.

  2. (2)

    When the CTE of the build-up film used in FCBGA substrate is designed to be close to that of the copper foil (18 ppm/°C), the degree of warpage can be decreased. The experimental results confirmed that when the CTE of the build-up film decreased from 39 to 19 ppm/°C, a value similar to the CTE of copper foil (18 ppm/°C), the degree of warpage can be reduced by 92%.

  3. (3)

    Similarly, warpage can be reduced by controlling the CTE of the FCBGA substrate core board, which consists of copper foil, epoxy resin, and glass fabric. In this study, CTE control techniques for FCBGA substrate core boards were investigated. These control techniques involve adjusting the RC, glass fabric type, filler ratio, and board material.

  4. (4)

    In this study, the key materials used for the FCBGA substrates were provided by the R&D centre of the Grace T.H.W. Group. These key materials included low-CTE, ultra-low loss build-up film from the GBF series (CTE of 17–22 ppm/°C), ultra-low-loss plates GA-688N and GA-688Q (Df<0.002); low-Dk, low-CTE glass fabrics; and quartz cloths used in FCBGA core boards. They help reduce FCBGA substrate warpage and improve the reliability of ASIC, CPU, and advanced GPU chips. They also help ensure system safety, as in the example of using a GPU chip as the core computing power source for modern autonomous vehicles and AI robots. While maintaining ultra-low loss for FCBGA substrates, these key materials contribute to improving the signal transmission speed and integrity of chips. Thus, they are excellent choices for the future packaging of advanced GPU chips.