Introduction

Bidirectional converters support power transfer in both directions, making them ideal for EVs, smart grids, UPS, aerospace, and renewable energy applications1,2,3. Their ability to interface sources with storage removes the need for separate converters, resulting in more compact designs and higher efficiency. Bidirectional DC–DC converters (BDCs) can be classified as either isolated or non-isolated. In isolated architectures, a high-frequency transformer facilitates the DC–AC–DC conversion process while ensuring galvanic isolation between the low-voltage side (LVS) and the high-voltage side (HVS). In applications where isolation is unnecessary, non-isolated BDCs are generally preferred owing to their reduced structural complexity and simplified control requirements.

Non-isolated converter configurations include Cuk, SEPIC/Zeta, coupled-inductor, conventional buck–boost, three-level4,5,6,7, multilevel, and switched-capacitor types8. For Cuk and SEPIC/Zeta designs, the cascaded two-stage arrangement leads to lower conversion efficiency9,10. While coupled-inductor converters can deliver high voltage gain by adjusting the turns ratio11, they face persistent issues with leakage inductance, and their power processing capability is constrained by the magnetic core capacity. A coupled-inductor-based modification of the SEPIC converter was proposed in12, achieving high efficiency, high voltage gain, and soft-switching operation, but at the expense of additional active switches and capacitors. Battery charging and discharging are typically managed by bidirectional DC-DC converters (BDDCs), which must provide high buck gain during charging and high boost gain during discharging, while minimizing or eliminating current ripple on the battery side13,14,15,16. A wide range of converter designs and control techniques have been developed to address source current ripple. Coupled-inductor high-gain converters can significantly suppress ripple by selecting an appropriate turns ratio, but this enables either high voltage gain or ripple cancellation, not both at once. Non-coupled-inductor converters aimed at low source current ripple are generally classified into two groups: methods that decrease ripple amplitude and those that completely eliminate it at a specific duty ratio17.

Switched-capacitor converters offer a straightforward structure, simple control, and high scalability. By directing capacitor charge and discharge through different paths, energy can be transferred between the low- and high-voltage sides to attain high voltage gain. Early single-capacitor bidirectional designs18,19 exhibited low efficiency, leading to the development of interleaved switched-capacitor converter20 aimed at minimizing input current ripple. An interleaved configuration can effectively suppress significant current ripple on the low-voltage side (LVS)21. Complete ripple cancellation, however, requires the duty cycle to be locked to a specific ratio determined by the interleaving phase count. Ripple injection circuits, classified as active or passive, offer another suppression method. In the active scheme22, a ripple mirror circuit offset the inherent LVS ripple. Yet, eliminating the ripple entirely necessitates a fixed duty cycle, thereby constraining the attainable voltage conversion range. Reference23 introduced a DC–DC converter using voltage multiplier cells, providing high conversion ratio and low voltage stress. However, attaining such high gain necessitates multiple multiplier cells, which reduces power density and raises cost. In other works24,25,26,27, coupled-inductor designs achieve high voltage gain by adjusting the turns ratio of the magnetic components. A persistent drawback is leakage inductance, which induces voltage spikes on the switches, requiring snubber circuits to recover the associated energy. Reference28 introduces an active filter for source current ripple suppression, consisting of two switches, an inductor, and two capacitors. Although the converter’s voltage gain is preserved, the added components increase size and lower power density. The filter capacitors are regulated by separate converters operating at different frequencies and duty cycles, necessitating additional control circuitry and an isolation transformer. In29, a synchronous-switching bidirectional DC–DC converter was studied for LV-side ripple elimination, though it produced high HV-side ripple and used many switches.

The main contributions of this work are as follows: the development of a converter topology capable of maintaining low current ripple on both the high- and low-voltage sides; improved voltage gain in step-up operation and reduced gain in step-down operation; and the introduction of a design free from coupled inductors and switched capacitors, thereby enhancing power density while mitigating problems associated with leakage inductance and inrush current. In summary, this work presents a new bidirectional high step-up/step-down DC–DC converter topology that achieves high voltage gain with low device stress. Unlike most existing converters, the proposed design is free from coupled inductors and switched-capacitor networks, resulting in a simpler structure, reduced component count, and higher overall efficiency.

In this paper, Sect.“The proposed bidirectional converter” presents the description of the proposed converter along with its operation in both step-up and step-down modes. The steady-state analysis and design equations are provided in Sect. “Steady-state analysis of the proposed converter”. In Sect. “Small-signal analysis and controller design of the converter”, the small-signal model of the proposed converter for both operating modes is developed, and stability considerations are discussed. To benchmark the proposed topology against prior works, a comprehensive comparison is conducted in Sect. “Comparative assessment with recent advances”. Finally, Sect. “Loss analysis of a bidirectional DC-DC converter” provides the experimental results of a 400 W prototype to validate the theoretical analyses.

The proposed bidirectional converter

The proposed bidirectional converter, depicted in Fig. 1, consists of five switches, three inductors, and three capacitors. In the forward mode, switches S1 and S2 are simultaneously triggered while switches S3 through S5 remain off. Conversely, in the backward mode, switches S3 and S4 are triggered in a similar manner, with S1 and S2 turned off. Therefore, a single PWM pulse is sufficient to control the converter in both operating modes. During state 2 of both step-up and step-down modes, the MOSFET body diodes conduct naturally when the corresponding switches are turned off, providing a freewheeling path for the inductor currents and ensuring continuous current flow.

Fig. 1
figure 1

Circuit schematic of the proposed bidirectional converter.

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Converter operation

For ease of analyzing the steady-state characteristics of the proposed converter, the following practical assumptions are applied: (a) all power semiconductor devices and energy storage elements are considered ideal, and the converter operates under continuous conduction mode (CCM); (b) the capacitances are sufficiently large such that the voltage across each capacitor remains essentially constant during each switching cycle. In each mode of operation, the converter functions in continuous conduction mode (CCM) and exhibits two separate switching modes. Figure 2 depicts the key waveforms in both the step-up and step-down operating modes. Figures 3 and 4 show the equivalent circuits of the converter in the step-up and step-down modes, respectively.

$$V_{C1}=V_{C2}=V_C$$
(1)
Fig. 2
figure 2

Representative waveforms of the proposed converter: (a) step-up operation; (b) step-down operation.

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$$\:{C}_{1}={C}_{2}={C}_{}$$
(2)
$$\:\frac{{di}_{L1}}{dt}=\frac{{V}_{L}}{{L}_{1}}$$
(3)
$$\:\frac{{di}_{L2}}{dt}=\frac{{V}_{C1}+{V}_{C2}}{{L}_{2}}$$
(4)
$$\:\frac{{di}_{L3}}{dt}=\frac{{V}_{C2}+{V}_{C3}-{V}_{H}+{V}_{C1}}{{L}_{3}}$$
(5)
$$\:\frac{{dV}_{C}}{dt}=-\frac{{i}_{L3}+{i}_{L2}}{C}$$
(6)
$$\:\frac{{dV}_{C3}}{dt}=\frac{{-i}_{L3}}{{C}_{3}}$$
(7)
$$\:\frac{{dV}_{H}}{dt}=\frac{\frac{{-V}_{H}}{{R}_{o}}{+i}_{L3}}{{C}_{oH}}$$
(8)
Fig. 3
figure 3

Equivalent circuit of the converter in step-up mode: (a) first state; (b) second state.

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Fig. 4
figure 4

Equivalent circuit of the converter in step-down mode: (a) first state; (b) second state.

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Step-up mode

State 1:

switches S1 and S2 remain ON, while S3, S4, and S5 are kept OFF. Under these conditions, inductors L1 and L3 store energy, whereas capacitors C1, C2, and C3 release their stored charge. During this period, the load is powered entirely by the output capacitor CoH. The corresponding state-space equations for the converter in this operating state are expressed as follows.

$$\:{V}_{C1}={V}_{C2}={V}_{C}$$
(9)

State 2:

With switches S1 and S2 turned off, the body diodes of S4, S5, and S3 conduct. During this interval, inductors L1 and L3 release their stored energy to the output, while capacitors C1, C2, and C3 are being charged. This mode concludes once the switches are turned on again.

$$\:\frac{{di}_{L1}}{dt}=\frac{{V}_{L}-{V}_{C}}{{L}_{1}}$$
(10)
$$\:\frac{{di}_{L2}}{dt}=\frac{-{V}_{C3}}{{L}_{2}}$$
(11)
$$\:\frac{{di}_{L3}}{dt}=\frac{-{V}_{H}}{{L}_{3}}$$
(12)
$$\:\frac{{dV}_{C}}{dt}=\frac{{i}_{L1}}{2C}$$
(13)
$$\:\frac{{dV}_{C3}}{dt}=\frac{{i}_{L2}}{{C}_{3}}$$
(14)
$$\:\frac{{dV}_{H}}{dt}=\frac{\frac{{-V}_{H}}{{R}_{o}}{+i}_{L3}}{{C}_{oH}}$$
(15)

Step-down mode

State1:

In this state, switches S4, S5, and S3 are in the on-state, while S1 and S2 remain off. Inductor L3 is energized, and with S1 and S2 turned off, capacitors C1 and C2 are effectively paralleled, delivering their stored energy to the output via L1. Simultaneously, capacitor C3 supplies energy to magnetize the coupled inductor. During this mode, both L1 and L3 undergo a linear charging process. The state-space representation of the converter in this operating mode is expressed as follows.

$$\:{V}_{C1}={V}_{C2}={V}_{C}$$
(16)
$$\:{C}_{1}={C}_{2}={C}_{}$$
(17)
$$\:\frac{{di}_{L1}}{dt}=\frac{{{V}_{C}-V}_{L}}{{L}_{1}}$$
(18)
$$\:\frac{{di}_{L2}}{dt}=\frac{{V}_{C3}}{{L}_{2}}$$
(19)
$$\:\frac{{di}_{L3}}{dt}=\frac{{V}_{H}}{{L}_{3}}$$
(20)
$$\:\frac{{dV}_{C}}{dt}=-\frac{{i}_{L1}}{2{C}_{}}$$
(21)
$$\:\frac{{dV}_{C3}}{dt}=-\frac{{i}_{L2}}{{C}_{3}}$$
(22)
$$\:\frac{{dV}_{L}}{dt}=\frac{-\frac{{V}_{L}}{{R}_{o}}{+i}_{L1}}{{C}_{o1}}$$
(23)

State 2:

During this stage, switches S4, S5, and S3 are in the off-state, causing the body diodes of S1 and S2 to conduct. Consequently, inductors L1 and L3 release their stored energy to the output, while capacitors C1, C2, and C3 are being energized.

$$\:\frac{{di}_{L1}}{dt}=\frac{-{V}_{L}}{{L}_{1}}$$
(24)
$$\:\frac{{di}_{L3}}{dt}=\frac{-2{V}_{C}}{{L}_{2}}$$
(25)
$$\:\frac{{di}_{L3}}{dt}=\frac{{V}_{H}-2{V}_{C}}{{L}_{3}}$$
(26)
$$\:\frac{{dV}_{C}}{dt}=\frac{{{i}_{L2}+i}_{L3}}{C}$$
(27)
$$\:\frac{{dV}_{C3}}{dt}=\frac{{i}_{L3}}{{C}_{3}}$$
(28)
$$\:\frac{{dV}_{L}}{dt}=\frac{\frac{{-V}_{L}}{{R}_{o}}{+i}_{L1}}{{C}_{o1}}$$
(29)

Steady-state analysis of the proposed converter

This section provides a comprehensive analysis of the proposed bidirectional converter, including its voltage gain in both modes of operation, the voltage and current stresses on the components, and the design equations for the passive elements.

Voltage gain

The voltage–second balance principle is applied to all three inductors of the circuit for both step-up and step-down operation modes. Based on these formulations, the expressions for the converter voltage gain in each mode are directly derived as follow.

$$\:{L}_{1}:\:{V}_{L}DT+\left({V}_{L}-{V}_{C}\right)\left(1-D\right)T=0$$
(30)
$$\:{V}_{C}={V}_{C1}={V}_{C2}=\frac{{V}_{L}}{(1-D)}$$
(31)
$$\:{L}_{2}:\:\left({V}_{C1}+{V}_{C2}\right)DT-{V}_{C3}\left(1-D\right)T=0$$
(32)
$$\:{V}_{C3}=\frac{2D{V}_{L}}{{(1-D)}^{2}}$$
(33)
$$\:{L}_{3}:\:\left({V}_{C1}+{V}_{C2}+{V}_{C3}-{V}_{H}\right)DT-{V}_{H}\left(1-D\right)T=0$$
(34)
$$\:{V}_{H}={(V}_{C1}+{V}_{C2}+{V}_{C3})D=\frac{2D{V}_{L}}{{(1-D)}^{2}}$$
(35)
$$\:\frac{{V}_{H}}{{V}_{L}}=\frac{2D}{{(1-D)}^{2}}$$
(36)

For step-down mode:

$$\:{L}_{1}:\:\left({V}_{C1}-{V}_{L}\right)DT+\left(-{V}_{L}\right)\left(1-D\right)T=0$$
(37)
$$\:{V}_{L}={DV}_{C1}$$
(38)
$$\:{L}_{2}:\:-{V}_{C3}DT+\left({V}_{C1}+{V}_{C2}\right)\left(1-D\right)T=0$$
(39)
$$\:{V}_{C3}=\frac{\left({V}_{C1}+{V}_{C2}\right)\left(1-D\right)}{D}$$
(40)
$$\:{L}_{3}:\:{V}_{H}DT+\left({V}_{H}{-(V}_{C1}+{V}_{C2}+{V}_{C3})\right)\left(1-D\right)T=0$$
(41)
$$\:{V}_{H}=\frac{{V}_{C1}+{V}_{C2}+{V}_{C3}}{1-D}$$
(42)
$$\:{V}_{C1}={V}_{C2}=\frac{{V}_{L}}{D}$$
(43)
$$\:\frac{{V}_{L}}{{V}_{H}}=\frac{{D}^{2}}{2(1-D)}$$
(44)

Figure 5 depicts the voltage gain profiles of the converter under both step-up (Fig. 5(a) and step-down (Fig. 5(b)) operating modes.

Fig. 5
figure 5

Voltage gain plot of the converter: (a) step-up mode; (b) step-down mode.

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Switch voltage stress

Using Kirchhoff’s voltage law for the switch loop when the switches are OFF, the maximum voltage across them can be easily determined from the following Eq. 

$$\:{V}_{S1}={{V}_{S4}={V}_{S5}=V}_{C}=\frac{{V}_{L}}{1-D}$$
(45)
$$\:{V}_{S2}={V}_{C2}+{V}_{C3}=\frac{(1+D){V}_{L}}{{(1-D)}^{2}}$$
(46)
$$\:{V}_{S3}={V}_{C1}+{V}_{C2}+{V}_{C3}=\frac{2{V}_{L}}{{(1-D)}^{2}}$$
(47)

Passive component design

Prior to selecting the capacitance values, it is essential to determine the average currents of the capacitors. By applying the ampere–second balance principle to capacitors C1, C2, C3, and Co, and utilizing Eqs. (2) and (4), the average currents of the inductors are derived as follows:

$$\:{I}_{L1}=\frac{2D{I}_{H}}{{(1-D)}^{2}}$$
(48)
$$\:{I}_{L2}=\frac{D{I}_{H}}{(1-D)}$$
(49)
$$\:{I}_{L3}={I}_{H}$$
(50)
$$\:{L}_{1}\ge\:\frac{{{V}_{L}(1-{D}_{H})}^{2}}{0.4{I}_{H}f}$$
(51)
$$\:{L}_{2}\ge\:\frac{{{V}_{C3}(1-{D}_{H})}^{2}}{0.2D{I}_{H}f}$$
(52)
$$\:{L}_{3}\ge\:\frac{10{D}_{H}{V}_{L}}{(1-{D}_{H}){I}_{H}f}$$
(53)
$$\:{C}_{1}={C}_{2}\ge\:\frac{{I}_{H}D}{f(1-D)\varDelta\:{V}_{C}}$$
(54)
$$\:{C}_{3}\ge\:\frac{{I}_{H}D}{f\varDelta\:{V}_{C3}}$$
(55)

Small-signal analysis and controller design of the converter

By presuming ideal characteristics for all semiconductor and passive elements, the averaged and small-signal representations are formulated using the state-space averaging technique. In the step-up configuration (Fig. 3(b)) as well as in the step-down configuration (Fig. 4(a)), conduction of S4 and S5 or their intrinsic diodes places C1 and C2 in parallel, thereby enforcing voltage equality between C1 and C2.

Modeling of the step-up operating mode

To analyze the dynamic behavior of the proposed bidirectional converter, the state-space averaging technique is employed. Considering ideal semiconductor and passive elements, two subintervals corresponding to switch ON and OFF states are modeled in step-up mode. By averaging these models over a switching cycle with duty ratio D the large‐signal model is expressed as below

$${A_{}}=\left[ {\begin{array}{*{20}{c}} 0&0&0&{ - \frac{{1 - D}}{{{L_1}}}}&0&0&0 \\ 0&0&0&{\frac{D}{{{L_2}}}}&{\frac{D}{{{L_2}}}}&{ - \frac{{1 - D}}{{{L_2}}}}&0 \\ 0&0&0&{\frac{D}{{{L_3}}}}&{\frac{D}{{{L_3}}}}&{\frac{D}{{{L_3}}}}&{ - \frac{1}{{{L_3}}}} \\ {\frac{{1 - D}}{{2{C_1}}}}&{ - \frac{D}{{{C_1}}}}&{ - \frac{D}{{{C_1}}}}&0&0&0&0 \\ {\frac{{1 - D}}{{2{C_2}}}}&{ - \frac{D}{{{C_2}}}}&{ - \frac{D}{{{C_2}}}}&0&0&0&0 \\ 0&{\frac{{1 - D}}{{{C_3}}}}&{ - \frac{D}{{{C_3}}}}&0&0&0&0 \\ 0&0&{\frac{1}{{{C_{OH}}}}}&0&0&0&{ - \frac{1}{{{R_O}{C_{OH}}}}} \end{array}} \right]$$
(56)
$$B=\left[ {\begin{array}{*{20}{c}} {\frac{{{V_L}}}{{{L_1}(1 - D)}}} \\ {\frac{{2{V_L}}}{{{L_2}{{(1 - D)}^2}}}} \\ {\frac{{2{V_L}}}{{{L_3}{{(1 - D)}^2}}}} \\ {\frac{{2D{V_L}}}{{{R_o}{C_1}{{(1 - D)}^4}}}} \\ {\frac{{2D{V_L}}}{{{R_o}{C_2}{{(1 - D)}^4}}}} \\ {\frac{{2D{V_L}}}{{{R_o}{C_3}{{(1 - D)}^3}}}} \\ 0 \end{array}} \right]$$
(57)
$$\begin{gathered} C=\left[ {\begin{array}{*{20}{c}} 0&0&0&0&0&0&1 \end{array}} \right] \hfill \\ D=\left[ 0 \right] \hfill \\ \end{gathered}$$
(58)
$$\:y+A\left(D\right)x=\dot{x}$$
(59)
$$\:Cx=B\left(D\right){V}_{L}$$
(60)
$${G_{vd,step - up}}(s)=\frac{{2.273*{{10}^9}{s^4} - 2.611*{{10}^{12}}{s^3}+8.124*{{10}^{16}}{s^2} - 3.704*{{10}^{19}}s+5.268*{{10}^{23}}}}{{{s^6}+45.45{s^5}+6.327*{{10}^7}{s^4}+2.669*{{10}^9}{s^3}+6.767*{{10}^{14}}{s^2}+2.338*{{10}^{16}}s+2.634*{{10}^{20}}}}$$
(61)

Modeling of the step-down operating mode

To investigate the dynamic performance of the proposed bidirectional converter in the step-down mode, the state-space averaging method is applied. Assuming ideal components, two switching intervals (ON and OFF states) are formulated, and their combination over a switching cycle with duty ratio D yields the corresponding large-signal model.

$$\begin{gathered} \hfill \\ A=\left[ {\begin{array}{*{20}{c}} 0&0&0&{\frac{D}{{{L_1}}}}&0&{ - \frac{1}{{{L_1}}}} \\ 0&0&0&{ - \frac{{(1 - D)}}{{{L_2}}}}&{\frac{D}{{{L_2}}}}&0 \\ 0&0&0&{ - \frac{{(1 - D)}}{{{L_3}}}}&0&0 \\ { - \frac{D}{{2C}}}&{\frac{{(1 - D)}}{C}}&{\frac{{(1 - D)}}{C}}&0&0&0 \\ 0&{ - \frac{D}{{{C_3}}}}&{\frac{{(1 - D)}}{{{C_3}}}}&0&0&0 \\ {\frac{1}{{{C_{OL}}}}}&0&0&0&0&{ - \frac{1}{{{R_O}{C_{OL}}}}} \end{array}} \right] \hfill \\ \end{gathered}$$
(62)
$$\begin{gathered} \hfill \\ B=\left[ {\begin{array}{*{20}{c}} {\frac{{{V_L}}}{{2(1 - D){L_1}}}} \\ {\frac{{{V_L}}}{{D(1 - D){L_2}}}} \\ {\frac{{{V_L}}}{{(1 - D){L_3}}}} \\ {\frac{{D{V_L}}}{{4{R_O}{C_{OL}}{{(1 - D)}^2}}}} \\ {\frac{{{D^2}{V_L}}}{{4{R_O}{C_3}{{(1 - D)}^2}}}} \\ 0 \end{array}} \right] \hfill \\ \end{gathered}$$
(63)
$$C=\left[ {\begin{array}{*{20}{c}} 0&0&0&0&0&1 \end{array}} \right]$$
(64)
$$D=\left[ 0 \right]$$
(65)
$${G_{vd}}(s)=\frac{{1.333e10{s^4} - 2.647e11{s^3}+3.008e18{s^2}+3.298e20s+2.743e25}}{{{s^6}+1024{s^5}+1.546*{{10}^8}{s^4}+1.107*{{10}^{11}}{s^3}+5.271*{{10}^{15}}{s^2}+9.753*{{10}^{17}}s+3.744*{{10}^{22}}}}$$
(66)

Dynamic behavior of the converter

Because the converter may exhibit nonminimum-phase behavior in step-up operation due to the presence of a right-half-plane zero, the crossover frequency ωc must be selected well below the RHP-zero frequency and also remain a small fraction of the switching frequency, i.e., ωc ≲ 0.2 ωz,RHP and ωc≪0.1 ωs. To ensure stable and well-damped closed-loop performance, a PI controller of the form CPI(s) = Kp+Ki/s = Kp(1 + ωi/s) with ωi = Ki/Kp is designed using loop-shaping. In the step-down operating mode, a PI controller is also adopted to regulate the output voltage and achieve stable closed-loop performance. Unlike the boost case, the buck configuration does not introduce a right-half-plane zero; therefore, the crossover frequency ωc can be selected higher, though it still must remain well below one-tenth of the switching frequency to ensure robustness, i.e., ωc≪0.1 ωs. The PI compensator maintains the same structure, CPI(s) = Kp+Ki/s = Kp(1 + ωi/s) where the zero is placed at ωi ≈ ωc/10 to improve phase margin and enhance low-frequency tracking. The proportional gain Kp is again tuned by enforcing unity open-loop gain at the chosen ωc. This procedure ensures that in the step-down mode the system achieves sufficient phase margin and disturbance rejection, while the integral term guarantees zero steady-state error in output voltage regulation.

Figure 6 depicts the control block diagram of the proposed bidirectional converter, whereas Figs. 7 shows the system’s Bode plots for the step-up and step-down modes, respectively, comparing the cases with and without the PI controller.

Fig. 6
figure 6

Schematic diagram of the control circuit of the proposed bidirectional converter.

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Fig. 7
figure 7

The Bode diagram of the proposed converter: (a) operation in step-up mode, (b) operation in step-down mode.

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Comparative assessment with recent advances

Table 1 provides a comparative evaluation of the proposed converter against previously reported topologies in terms of voltage gain in both operating modes, component count, current ripple on both sides, and overall efficiency. Converters20,24,30,31, and32 exhibit both lower voltage gain and higher ripple at the high-voltage port, necessitating larger filter capacitors. Although converters33,34,35 maintain low current ripple on both sides, their achievable gain remains limited. As illustrated in Fig. 8, the proposed converter demonstrates superior performance in both step-up and step-down operations, reducing the duty ratio in step-up mode while increasing it in step-down mode. Additionally, converter20 incurs considerable conduction losses due to its diode-based structure, whereas converter27 is unsuitable for low-voltage applications such as batteries or fuel cells because of its high input-side ripple. Figure 8 illustrates the comparative voltage gain characteristics for both operating modes, where (a) corresponds to the step-up mode and (b) represents the step-down mode. Figure 9 compares the maximum switch voltage stress (Fig. 9(a)) and the maximum switch current stress (Fig. 9(b)) among the converters listed in Table 1. As demonstrated in Fig. 9, the proposed converter achieves superior performance by substantially reducing the normalized switch voltage and current stress, leading to lower conduction losses and component ratings.

Fig. 8
figure 8

Comparative plots of the converter: (a) voltage gain comparison in step-up mode, (b) voltage gain comparison in step-down mode.

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Fig. 9
figure 9

Comparative plots of the converter: (a) normalized switch voltage stress in step-up mode, (b) normalized switch current stress in step-up mode.

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Table 1 Performance comparison between the proposed converter and other previously developed converters.
Full size table

Figure 10 presents a comparative analysis of the estimated cost and power density for the proposed converter and several state-of-the-art topologies reported in the literature. Each converter is represented by two adjacent bars corresponding to the cost (in USD) and the power density (in W/cm³). As illustrated, the proposed design exhibits a balanced performance achieving a significantly higher power density while maintaining a moderate overall cost compared with most reference converters.

Fig. 10
figure 10

Comparison of estimated cost and power density among the proposed converter and other reported topologies.

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Loss analysis of a bidirectional DC-DC converter

This section presents a detailed loss analysis of a bidirectional DC-DC converter operating in step-up and step-down mode. The goal is to calculate the conduction and switching losses of MOSFETs, conduction losses of body diodes, copper and core losses of the inductors, and losses in the capacitors, as well as to estimate the overall efficiency.

Step-up mode losses

MOSFET Conduction Losses: The conduction loss of each MOSFET is calculated using:

$$\:{P}_{Con\left(Sw\right)}=\left(\sum\nolimits_{i=1}^{2}{{I}_{RMS-Si}}^{2}{R}_{DS-i}\right)=0.04*\left({4.36}^{2}+{2.14}^{2}\right)=1.085W$$
(67)

MOSFET Switching Losses: The switching losses due to turning on and off the MOSFETs are estimated by:

$$\begin{aligned}\:{P}_{Switching\left(Sw\right)} & =\left(\sum\nolimits_{i=1}^{2}{{\frac{1}{2}I}_{DS-Si}}^{}{V}_{DS-i}({t}_{r}+{t}_{f}){f}_{sw}\right)\\ & =0.5\text{*}\left(4.36\text{*}120+2.14\text{*}345\right)\text{*}180\text{*}{10}^{-9}\text{*}50\text{*}{10}^{3}=4.5\text{W}\end{aligned}$$
(68)

MOSFET Capacitive Turn-On Losses: The capacitive turn-on (drain-to-source capacitance) losses are calculated using:

$$\begin{aligned}\:{P}_{Capacitive\left(Sw\right)} & =\left(\sum\nolimits_{i=1}^{2}{{\frac{1}{2}.C}_{Oss-Si}}^{}{{V}^{2}}_{DS-i}{f}_{sw}\right)\\ & =0.5*603*{10}^{-12}*50*{10}^{3}*({120}^{2}+{345}^{2})=3.17W\end{aligned}$$
(69)

Body Diode Conduction Losses: Conduction losses for the MOSFET body diodes are estimated by:

$$\:\sum\nolimits_{i=3}^{5}{{I}_{av-{D}_{Si}}}^{}{V}_{F}=\left(1.2+0.99+1.011\right)*1.3=4.29W$$
(70)

Inductor Copper Losses: The copper losses in the inductors are computed as:

$$\begin{aligned}\:{P}_{Con,Inductors} & ={\sum\nolimits_{i=1}^{3}{{{R}_{L1i}I}_{RM{S}^{{\prime\:}}L1i}}^{2}}_{} \\ & =0.015*{8.4}^{2}+0.04*{0.46}^{2}+0.2*{1.11}^{2}=1.79W\end{aligned}$$
(71)

Inductor Core Losses The core losses are estimated conservatively based on ferrite volume and typical loss density at 50 kHz:

$$\:{{P}_{Core,Inductors}=\sum\nolimits_{i=1}^{3}f*{k}_{i}*{A}_{e}*{l}_{e}*V}_{Core}^{b}*\varDelta\:B{\left(\frac{{V}_{on}}{N{A}_{e}f\varDelta\:B}\right)}^{\alpha\:-1}=0.73W$$
(72)

The total core loss for the three Ferrite inductors is modeled and verified to be 0.73 W using the comprehensive loss equation at a switching frequency 50 kHz. The calculation incorporates the core’s effective area (Ae), set at 0.5 * 10− 4 m2, and a peak-to-peak flux density change \(\:\varDelta\:B=0.1T\). The key loss parameters for the Ferrite material are the frequency coefficient \(\:\alpha\:\), approximately 2.5 the volume coefficient (b), approximately 1, and the material coefficient (k), which is determined by the selected material and design to be 4.61 * 105.

Capacitor Losses: Capacitor ESR losses are calculated using:

$$\begin{aligned}\:{P}_{Cap} & =\sum\nolimits_{i=1}^{5}{R}_{Ci}{{I}_{RM{S,}^{}Ci}}^{2} \\ & =0.02*{1.5}^{2}+2*0.015*{0.8}^{2}+2*{0.49}^{2}*0.05+0.015*{0.574}^{2}=0.11W\end{aligned}$$
(73)

In this mode, the total converter loss is obtained from theoretical calculations by summing the conduction and switching losses of the semiconductors, the copper and core losses of the inductors, and the ESR losses of the capacitors. The efficiency is then expressed as

$$\:{Eff}_{boost}=\frac{{P}_{o}}{{P}_{o}+{P}_{loss}}=\frac{400}{400+15.67}\approx\:96.23\%$$
(74)

Step-down mode losses

The same methodology applied for boost mode is also used to analyze the converter in step-down mode at full load. In this configuration, three switches are actively conducting while the body diodes of the remaining two switches carry current. The total losses are calculated by summing the conduction and switching losses of the active MOSFETs, the losses in the body diodes, the copper and core losses of the inductors, and the ESR losses of the capacitors. The efficiency is then determined as the ratio of the output power to the total of output power and losses. The detailed formulas used for each component’s loss calculation are presented. The loss analysis, detailing the distribution for both step-up and step-down modes, is summarized in the breakdown shown in Fig. 11.

$$\:{P}_{Con\left(Sw\right)}=\left(\sum\nolimits_{i=1}^{3}{{I}_{RMS-Si}}^{2}{R}_{DS-i}\right)=0.27*{1.11}^{2}+2*\:0.04*{2.08}^{2}=0.68W$$
(75)
$$\begin{aligned}\:{P}_{Switching\left(Sw\right)} & =\left(\sum\nolimits_{i=1}^{3}{{\frac{1}{2}I}_{DS-Si}}^{}{V}_{DS-i}({t}_{ri}+{t}_{fi}){f}_{sw}\right) \\ & =0.5*1.11*160*245*{10}^{-9}*50*{10}^{3}+2*0.5*0.97*120*180*{10}^{-9}*50*{10}^{3}=2.1W\end{aligned}$$
(76)
$$\begin{aligned}\:{P}_{Capacitive\left(Sw\right)} & =\left(\sum\nolimits_{i=1}^{3}{{\frac{1}{2}.C}_{Oss-Si}}^{}{{V}^{2}}_{DS-i}{f}_{sw}\right) \\ & =0.5*870\text{*}{10}^{-12}*{180}^{2}\text{*}50\text{*}{10}^{3}+2*0.5\text{*}603\text{*}{10}^{-12}{*120}^{2}\text{*}50\text{*}{10}^{3}=1.51W\end{aligned}$$
(77)
$$\:\sum\nolimits_{i=1}^{2}{{I}_{av-{D}_{Si}}}^{}{V}_{F}=\left(1.11*1.3+3.32*1.3\right)=5.76W$$
(78)
$$\:{P}_{Con,Inductors}={\sum\nolimits_{i=1}^{3}{{{R}_{L1i}I}_{RM{S}^{{\prime\:}}L1i}}^{2}}_{}=0.02*{8.33}^{2}+0.07*{1.26}^{2}+0.07*{1.23}^{2}=1.63W$$
(79)
$$\:{{P}_{Core,Inductors}=\sum\nolimits_{i=1}^{3}f*{k}_{i}*{A}_{e}*{l}_{e}*V}_{Core}^{b}*\varDelta\:B{\left(\frac{{V}_{on}}{N{A}_{e}f\varDelta\:B}\right)}^{\alpha\:-1}=0.64$$
(80)
$$\begin{aligned}\:{P}_{Cap} & =\sum\nolimits_{i=1}^{4}{R}_{Ci}{{I}_{RM{S,}^{}Ci}}^{2}\\ & =0.02*{1.11}^{2}+0.015*{1.15}^{2}+{0.015*0.816}^{2}+0.015*{1.02}^{2}+0.05*{0.632}^{2}=0.09W\end{aligned}$$
(81)
$$\:{Eff}_{buck}=\frac{{P}_{o}}{{P}_{o}+{P}_{loss}}=\frac{400}{400+12.41}\approx\:96.99\%$$
(82)
Fig. 11
figure 11

Loss breakdown for (a) step-up operation and (b) step-down operation.

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Experimental verification

For experimental validation of the theoretical analyses, a laboratory prototype of the proposed converter was built, featuring a 400 W power rating and compact dimensions of 7*10*3.5 cm3. The detailed parameters of this prototype are listed in Table 2, and a photograph of the hardware implementation is shown in Fig. 12. Experimental results for both step-up and step-down operation modes are provided in Figs. 13 and 14, respectively. Specifically, Fig. 13(a) presents the gate voltage waveforms of switches S1 and S2, while Fig. 13(b) illustrates the drain–source voltage and current of S1. The current waveform of inductor L1 is presented in Fig. 13(c). The drain–source voltage and current of switch S2 are illustrated in Fig. 13(d), whereas Fig. 13(e) provides the measured input and output voltage profiles of the converter. The dynamic response of the converter to load variations, confirming the effectiveness of the control loop, is shown in Fig. 13(f). Likewise, for the step-down mode, Fig. 14(a) shows the gate voltage waveforms of switches S3 and S4, and Fig. 14(b) depicts their drain–source voltages. The drain-source currents of switches S3 and S4 are displayed in Fig. 14(c), and the corresponding current for S5 is illustrated in Fig. 14(d). Capacitor voltage waveforms (C1–C3) are presented in Fig. 14(e), and the dynamic load response is illustrated in Fig. 14(f). The dynamic response characteristics of the converter to input voltage changes are illustrated in Fig. 15, showing transient behavior under both sudden (Figs. 15(a), 15(b)) and linear (Fig. 15(c)) changes in the input voltage. Specifically, Fig. 15(c) depicts step-up operation where the input voltage rises steadily from 40 V to 100 V while the output voltage remains fixed at 360 V. Altogether, these experimental findings corroborate the theoretical analysis.

Fig. 12
figure 12

Laboratory implementation of the proposed converter.

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Fig. 13
figure 13

Step-up mode practical results: (a) gate voltage of S1, S2 (b) drain-source voltage and current of S1 (c) current of L1 (d) drain-source voltage and current of S2 (e) regulated output voltage and input voltage (f) dynamic response of the proposed converter.

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Fig. 14
figure 14

Step-down mode practical results: (a) gate voltage of S3, S4 (b) the drain-source voltage of S3 and S4 (c) the drain-source current of S3 and S4 (d) the drain-source current of S5 (e) voltages across capacitors C1, C2, and C3 (f) dynamic response of the proposed converter.

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Fig. 15
figure 15

Dynamic response of the converter to input voltage variations: (a) abrupt input voltage change from 40 V to 100 V in step-up mode; (b) abrupt high-voltage side change from 480 V to 300 V in step-down mode; and (c) linear input voltage change from 40 V to 100 V in step-up mode.

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Table 2 Parameter specifications utilized in the experimental setup.
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Converter efficiency

According to Fig. 16, the efficiency of the proposed bidirectional converter improves as the output power increases in both the step-up and step-down modes. At light loads, conduction and switching losses play a more dominant role in lowering efficiency, but their influence becomes less pronounced as the load grows, resulting in higher overall performance. When comparing the two modes, the step-down operation exhibits slightly better efficiency than the step-up operation, mainly due to fewer active switch turn-ons, lower circulating currents, and therefore reduced losses. In general, the converter maintains an efficiency 96.3% in step-down mode and 96% in step-up mode at full load, confirming its effectiveness and suitability for practical applications.

Fig. 16
figure 16

Efficiency curves of the proposed converter in both step-up and step-down modes under varying output load conditions.

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Conclusion

This study presents a novel bidirectional DC–DC converter capable of delivering very high voltage gain in the step-up mode and substantially reduced voltage gain in the step-down mode. The design employs only two switches operating concurrently in step-up mode and three switches operating together in step-down mode, which simplifies the control structure. Moreover, the proposed configuration achieves low current ripple on both input and output sides, enabling the use of smaller filter capacitors. Experimental results validate the effectiveness of the converter, showing excellent efficiency of 96% in step-up operation and 96.3% in step-down operation.