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Yttrium-doping-induced metallization of molybdenum disulfide for ohmic contacts in two-dimensional transistors

Nature Electronics volume 7, pages 545–556 (2024) Cite this article

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Abstract

The van der Waals systems could be used to overcome the issue of Fermi-level pinning in contacts of transistors based on two-dimensional semiconductors. However, the lack of advanced-node-lithography-compatible methods limits the use of such materials in wafer-scale integrated manufacturing. Here we report a yttrium-doping approach to convert semiconducting molybdenum disulfide (MoS2) into metallic MoS2. The approach, which is compatible with advanced-node wafer-scale integration, improves the band alignment and provides ohmic device contacts. It is based on a solid-state-source three-step doping method involving plasma, deposition and annealing, and can provide ångström-thickness surface doping. The yttrium-doped MoS2 acts as a metallic buffer that improves charge carrier transfer from the metal electrode to semiconducting MoS2. With this approach, we fabricate self-aligned, 10-nm-channel-length MoS2 field-effect transistors on two-inch wafers with an average contact resistances of 69 Ω µm and total resistances of 235 Ω µm. Our devices exhibit an ON-current density of 1.22 mA µm–1 at a drain voltage of 0.7 V, a ballistic ratio of 79% and a transconductance of 3.2 mS µm–1.

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Fig. 1: Illustration and theoretical calculations of doping transformation and metallic Y-MoS2 ohmic contact.
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Fig. 2: Characterization of atomic-layer Y-doping metallic contact technology.
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Fig. 3: Structure and contact properties of ballistic MoS2 FETs.
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Fig. 4: Wafer-scale fabrication and comparison of MoS2 FETs.
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The data that support the findings of this study are available from the corresponding authors upon reasonable request.

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Acknowledgements

This research was supported by the National Key Research & Development Program of China (grant nos. 2021YFA0717400 and 2021YFA1202900) and the National Science Foundation of China (grants 61888102, 61971009 and 62122006) and Peking Nanofab Laboratory.

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Author notes

  1. These authors contributed equally: Jianfeng Jiang, Lin Xu.

Authors and Affiliations

  1. Key Lab for the Physics and Chemistry of Nanodevices and Center for Carbon-based Electronics, School of Electronics, Peking University, Beijing, China

    Jianfeng Jiang, Lin Xu, Chenguang Qiu & Lian-Mao Peng

  2. Beijing National Laboratory for Condensed Matter Physics and Institute of Physics, Chinese Academy of Sciences, Beijing, China

    Luojun Du, Lu Li & Guangyu Zhang

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  1. Jianfeng Jiang
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  2. Lin Xu
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  7. Lian-Mao Peng
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Contributions

C.Q. and L.-M.P. proposed and supervised the project. J.J., C.Q. and L.-M.P. conceived the idea and designed the theory and experiment. J.J. performed the Y-MoS2 material STEM, Raman and XPS characterizations; device fabrication and device characterization; and data analysis under the supervision of C.Q. and L.-M.P. L.L., L.D. and G.Z. provided the two-inch wafer-scale MoS2 materials. L.X. provided the first-principles calculation and model fitting. J.J., C.Q., L.X. and L.-M.P. analysed the experimental results and modeling results. J.J., C.Q., L.X. and L.-M.P. co-wrote the manuscript. All authors commented on and discussed this work.

Corresponding authors

Correspondence to Chenguang Qiu or Lian-Mao Peng.

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Extended data

Extended Data Fig. 1 Simulation of band structure and in-plane heterojunction.

a, Calculated band structure for intrinsic 2H MoS2. b, Calculated band structure for intrinsic semimetallic 1T MoS2. c, Calculation band structures for atomic-layer Y-doping MoS2 with 2H phase, metallic properties with zero bandgap and workfunction is 2.8 eV. d, Calculation band structures for atomic-layer Y-doping MoS2 with 1T phase, metallic properties with zero bandgap and workfunction is 4.0 eV.e, On the right is the PLDOS of in-plane heterojunction of metallic Y-MoS2 and 2H-MoS2, and on the left is the transmission spectra of the in-plane heterojunction.

Extended Data Fig. 2 Layer-by-layer epitaxy of MoS2 wafers and thickness dependent electrical characteristics.

a, Photograph of 2-inch wafers, including the sapphire (0001) substrate, monolayer, and trilayer MoS2 wafers. b, Photographs and scanning transmission electron microscopy image of monolayer MoS2. Scale bars, 30 μm and 4 nm. c, Photographs and scanning transmission electron microscopy image of trilayer MoS2. Scale bars, 30 μm and 4 nm. The trilayer MoS2 wafers were partially topped by 4-layer area (20%–30%)37. The MoS2 wafers have excellent crystal structures and atomically sharp interfaces. The material above the MoS2 is HfO2 dielectrics, which provides different interfacial conditions and a more dopant-free environment than the metal layer, resulting in clearer imaging16,37. d and e, AFM amplitude images of the mono- and trilayer MoS2 wafers. The blue curve and the red curve show the mono- and trilayer, respectively. Scale bars, 100 nm. f, Raman spectra of the as-grown mono- and trilayer MoS2 wafers. Raman A1g-E12g splitting (Δ) of approximately 20 cm−1 and 24 cm−1 confirmed that the MoS2 films were mono-layer and tri-layer. g, Comparison of transfer characteristics of a monolayer, bilayer, and trilayer dual-gate MoS2 FETs with LCH= 20 nm at VDS= 0.1 V. h, Comparison of linear-output characteristics of monolayer, bilayer, and trilayer dual-gate MoS2 FETs with LCH= 20 nm and other reported MoS2 FETs30,31. i, Comparison of the total resistance of our monolayer, bilayer, and trilayer dual-gate MoS2 FETs with LCH= 20 nm and other reported MoS2 FETs.

Extended Data Fig. 3 Cross-sectional STEM and EELS maps of different metal/MoS2 contact conditions.

a, Cross-sectional STEM and EELS maps of vdWs contact between Pt metal (low-energy deposition) and trilayer MoS2. The green, yellow and purple maps of EELS represent Mo, S, and Pt elements, respectively. Scale bar of STEM, 2 nm. Scale bar of EELS map, 0.5 nm. b, Cross-sectional STEM and EELS maps of Y/Ti/Au and trilayer MoS2 contact without plasma treatment and annealing. The green, yellow, and red maps of EELS represent Mo, S, and Y elements, respectively. Scale bar of STEM, 2 nm. Scale bar of EELS map, 0.5 nm. c, Cross-sectional STEM and EELS maps of Y/Ti/Au and trilayer MoS2 contact with plasma-deposition-annealing (PDA) process. The green, yellow, and red maps of EELS represent Mo, S, and Y elements, respectively. Scale bar of STEM, 2 nm. Scale bar of EELS map, 0.5 nm. 1) The STEM image of Pt-MoS2 contact exhibited an atomic clean and sharp interface as well as an obvious vdWs gap of ~ 2 Å, and the element distribution of EELS maps also suggested the Pt atoms did not diffuse into the MoS2 in Extended Data Fig. 3a. The presence of a vdWs gap revealing weak-coupling contact affects the carrier transfer efficiency between the metal electrode and 2D MoS2; 2) For Y/Ti/Au-MoS2 contact system, there is no gap between metal and 2D MoS2 in the STEM images of Extended Data Fig. 3b and c, and the active Y atoms diffused into the MoS2 in the element distribution of EELS maps. Thus, these direct contact between metal and 2D semiconductors with atomic diffusion and without gap belong to a strong coupling system; 3) The Y/Ti/Au-MoS2 contacts without plasma and annealing processes exhibited only a light doping and weak atom injection due to the lack of sufficient injection sites and energy in Extended Data Fig. 3b, whereas Y/Ti/Au-MoS2 contacts with PDA proposed by us show a heavy and effective doping and stronger coupling (Extended Data Fig. 3c).

Extended Data Fig. 4 Comparison of transfer characteristics under various temperatures for ballistic MoS2 FETs with different contacts.

a, Transfer characteristics of a 10-nm ballistic MoS2 FET using a conventional Ti/Au metal contact, demonstrating a Schottky contact in a ballistic FET. b, Transfer characteristics of a 10-nm ballistic MoS2 FET using an intrinsic undoped 1T MoS2 contact, demonstrating a Schottky contact in a ballistic FET. Intrinsic 1T MoS2 was obtained via using a low-power argon plasma treatment (for 40 s), which is consistent with previous reports34. c, Transfer characteristics of a 10-nm ballistic MoS2 FET using an atomic-layer Y-doping metallic MoS2 contact, showing a true ohmic contact in a ballistic FET.

Extended Data Fig. 5 Typical electrical characteristics of 10-nm and 20-nm gate-length ballistic MoS2 FETs.

a, Output characteristics, transfer characteristics at VDS= 0.1, 0.3, 0.5, and 0.7 V, including SS and DIBL, and the corresponding transconductances of three typical 10-nm gate-length ballistic MoS2 FETs. b, Output characteristics, transfer characteristics at VDS= 0.1, 0.3, 0.5, and 0.7 V, including SS and DIBL, and the corresponding transconductances of three typical 20-nm gate-length ballistic MoS2 FETs.

Extended Data Fig. 6 Transmission-line-method (TLM) statistics.

a, The top-view SEM images of 15 sets of MoS2 FETs with dual-gate configurations for the TLM method. The channel length LCH are 90 nm, 180 nm, 280 nm, 380 nm, and 480 nm, separately. Scale bar, 500 nm. b, The ID versus channel length from the 15 devices at VDS= 0.1 V and VOV = 1 V. c, The corresponding total resistance versus channel length in 15 sets of MoS2 FETs, leading to an average RC value of 69 ± 13 Ω·μm and a minimum RC value of 43 ± 17 Ω·μm. d, Cumulative distribution function (CDF) plot showing the contact resistance RC and error bar from TLM devices. Each data point on each curve is from TLM analysis and the shaded regions represent the corresponding standard error. The median RC value is 69 ± 19 Ω·μm.

Extended Data Fig. 7 Electrical stability of the MoS2 FETs with the atomic-layer Y-doping contact technology.

a, Transfer characteristics of the dual-gate MoS2 FET with LCH= 20 nm measured at different temperatures. The black curve of the dual-gate MoS2 FET at VDS= 0.7 V is the first measurement at the temperature of 293 K (initial curve). The red curve of the dual-gate MoS2 FET at VDS= 0.7 V is the second measurement at a high temperature of 400 K. The blue curve of the dual-gate MoS2 FET at VDS= 0.7 V is the third measurement at the temperature of 293 K (after the high temperature of 400 K measurement). b, Transfer characteristics of a dual-gate tri-layer MoS2 FET at LCH= 10 nm with top-gate stack encapsulation in ambient conditions over 10 weeks (70 days). c, The extracted on-current density (ID) values of a dual-gate tri-layer MoS2 FET at LCH= 10 nm with top-gate stack encapsulation, with VDS= 0.7 V and VGS= 1 V, in ambient conditions over 10 weeks (70 days). d, The extracted SS of a dual-gate tri-layer MoS2 FET at LCH= 10 nm with top-gate stack encapsulation in ambient conditions over 10 weeks (70 days). e, The extracted Rtotal of a dual-gate tri-layer MoS2 FET at LCH= 10 nm with top-gate stack encapsulation in ambient conditions over 10 weeks (70 days). There is a slight degradation of the on-current and total resistance which is due to the slight shift of the threshold voltage rather than the contact degradation; meanwhile, SS remains approximately constant.

Extended Data Fig. 8 Statistical results of short-channel MoS2 FETs.

a, Typical SEM image of dual-gate tri-layer MoS2 FETs with LCH= 10 nm and LCH= 20 nm. Scale bar, 400 nm. b, Transfer characteristics of 50 individual fabricated MoS2 FETs with LCH= 10 nm. c, Transfer characteristics of 200 individual fabricated MoS2 FETs with LCH= 20 nm. d, Statistical histogram of subthreshold swing (SS). Red and orange colors denote MoS2 FET with LCH= 10 nm (50 devices) and LCH= 20 nm (200 devices). e, Statistical histogram of ID when VDS= 0.7 V and VGS= 1 V from 250 devices. Red and orange colors denote MoS2 FET with LCH= 10 nm (50 devices) and LCH= 20 nm (200 devices). For the 200 fabricated dual-gate tri-layer MoS2 FETs with LCH= 20 nm, the minimal SS and average SS are 61 mV/Dec and 67 mV/Dec, respectively, and the average on-current density is 0.76 mA/μm; for the 50 fabricated dual-gate tri-layer MoS2 FETs with LCH= 10 nm, the minimal SS and average SS are 74 mV/Dec and 83 mV/Dec, respectively, and the average on-current density is 0.84 mA/μm. Channel length scaled down from 20 nm to 10 nm with a 23.9 % degradation in average SS and a 10.5% increase in average on-current density. These results are consistent with the scaling performance trend of transistors4,45. f, Cumulative distribution function (CDF) plot showing the ID in 10 nm channel length devices and 20 nm channel length from devices at VDS=0.7 V and VGS= 1 V from e. The median ID for 10 nm channel length devices and 20 nm channel length devices are 0.845 mA/μm and 0.732 mA/μm, respectively. When the transistor is operating in the quasi-ballistic transport mode instead of diffusion transport mode, the carriers transport hardly suffers from the scattering in the channel, and channel resistance changes slightly with channel length. Even for our 20 nm channel length MoS2 device, the ballistic ratio is already as high as 74% (79% for our 10 nm MoS2 device). Thus, the performance does not have a significant boost when channel length decreases from 20 nm to 10 nm for quasi-ballistic devices.

Extended Data Fig. 9 Short-channel MoS2 FETs with different configurations.

a and b, The TCAD simulation of tri-layer MoS2 FETs with single-top-gate, single-back-gate and dual-gate configurations at Ltop-gate=10 nm and Lback-gate= 16 nm. The orange transfer characteristic is the single-top-gate MoS2 FET, the blue transfer characteristic is single-back-gate MoS2 FET, and the red transfer characteristic is dual-gate MoS2 FET. c, The experiment of tri-layer MoS2 FETs with single-top-gate, single-back-gate and dual-gate configurations at LCH= 20 nm. The orange transfer characteristic is the single-top-gate MoS2 FET, the blue transfer characteristic is single-back-gate MoS2 FET, and the red transfer characteristic is dual-gate MoS2 FET. d, Transfer characteristics of 100 fabricated dual-gate MoS2 FETs (red curves) and 100 fabricated single-back-gate MoS2 FETs (grey curves) at LCH= 20 nm. e and f, The top-view SEM images of tri-layer MoS2 FETs with single-back-gate configuration (before top-gate fabrication) and dual-gate configuration (after top-gate fabrication) at LCH= 20 nm. g, Statistical histogram of SS from 100 individual fabricated dual-gate MoS2 FETs at LCH= 20 nm. h, Statistical histogram of SS from 100 individual fabricated single-back-gate MoS2 FETs at LCH= 20 nm. i, Statistical histogram of ID when VDS= 0.7 V and VGS= 1 V from 100 fabricated dual-gate MoS2 FETs at LCH= 20 nm. j, Statistical histogram of ID when VDS= 0.7 V and VGS= 1 V from 100 fabricated single-back-gate MoS2 FETs at LCH= 20 nm.

Extended Data Fig. 10 Self-heating effect.

a, Thermal conductivity comparison of conventional MoS2 FET with single-back-gate (air and SiO2/SiNx on each side) and our MoS2 FET with ultra-thin HfO2 and dual-gate configuration. b, The output characteristics of a tri-layer MoS2 FET with dual-gate configuration. From top to bottom, VGS= 1 V to 0.3 V with 0.1 V steps. The color solid lines and hollow points are the results of the D.C. and pulse I-V measurements, respectively.

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Jiang, J., Xu, L., Du, L. et al. Yttrium-doping-induced metallization of molybdenum disulfide for ohmic contacts in two-dimensional transistors. Nat Electron 7, 545–556 (2024). https://doi.org/10.1038/s41928-024-01176-2

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