Low-temperature wafer-scale growth of ultrathin tungsten disulfide for bifunctional interconnect barriers and liners

Abstract

In the future, the miniaturization of integrated circuits will require copper wires to be scaled down in the back-end-of-line (BEOL) process. This will, in turn, require a scaling down of the barrier and liner coatings that prevent copper diffusion and ensure metal adhesion to the dielectric. Here we show that thin (<1 nm) and conformal tungsten disulfide (WS₂) layers can be grown on the wafer-scale using thermal atomic layer deposition without plasma at BEOL-compatible temperatures (350 °C) and can function as both barriers and liners for interconnects. We show that the WS₂ can reduce the resistivity of 10-nm-thick copper films by more than six orders of magnitude compared with a reference system (without the WS₂ layer) due to the improved wettability of copper. Monolayer WS₂ can prevent copper diffusion into silicon dioxide (SiO₂) under thermal stress, and it is projected to improve wire lifetimes under electrical stress. Density functional theory calculations also highlight the potential of multilayer WS₂ films as diffusion barriers due to misaligned grain boundaries.

Main

Integrated circuits (ICs) rely on networks of wires interconnecting the active IC components that perform logic and memory functions. In standard ICs, these networks constitute the back end of line (BEOL): a stacked structure of metal wires embedded in dielectric layers laid on top of the active semiconductor components (such as transistors) that constitute the front end of line (Fig. 1a). As the size of ICs has shrunk, advances in the performance of these metal interconnects have been driven by the integration of new materials. For example, aluminium (Al) interconnects were eventually replaced with copper (Cu) as the industry-standard main wire metal in the 1990s due to the high resistivity of Al in smaller interconnect sizes and its propensity to electromigration¹. This material switch increased the complexity of the overall interconnect structure, as more layers must be placed between the Cu/dielectric contact to address the high diffusivity and poor adhesion of Cu on industry-relevant dielectric materials. These two extra layers are called the barrier and the liner and are typically made of tantalum nitride (TaN) and tantalum (Ta), respectively.

Fig. 1: BEOL components and requirements for further miniaturization.

a, Schematic of a multilayer BEOL structure with a focus on the Cu/dielectric interface and scenarios for further interconnect downscaling. b, BEOL requirements for material integration as a bifunctional barrier and liner layer. c, Step coverage versus deposition temperature for WS₂ reported in recent works in the literature (references given at the top) and in our approach (red star). Shaded areas correspond to typical ranges for different growth methods, including chemical vapour deposition and physical vapour deposition^{14,37,38,39,40,41,42,43,44,45,46}. d, Representative Raman spectrum of our ALD-grown WS₂. e, Cross-sectional phase-contrast TEM image of monolayer WS₂ grown using our ALD process. Yellow arrows show the single-layer WS₂ film and its thickness. f, Photograph of the ALD-grown WS₂ over a 200 mm SiO₂/Si wafer (top) and the corresponding Raman map (bottom) of the peak separation Δω demonstrating the film uniformity. Complete wafer mapping from 504 spectra is shown in Supplementary Section 2. g, Plan-view STEM image of polycrystalline WS₂ with several grains marked. A hexagonal lattice composed of W atomic positions is observed in the upper left corner. CVD, chemical vapour deposition; FEOL, front end of line; PVD, physical vapour deposition.

The need for the barrier/liner bilayer creates challenges for modern electronics given that the migration of Cu atoms is one of the main failure mechanisms in interconnects, even at the current technology node of 5 nm. As the semiconductor industry advances towards the 3-nm technology node, the interconnect half pitches and wire diameters will reach a sub-20-nm region². At that point, the barrier/liner bilayer itself would occupy a substantial fraction (up to 50%) of the cross section of the wire because the absolute thickness of Ta/TaN must be ≥4 nm to maintain effective barrier properties^2,3 (Fig. 1a). This would lead to a substantial increase in the wire resistance (more than 200% for a wire of thickness 16 nm; for example, ref. ²) and, in turn, a slowing down of ICs due to the increased resistor–capacitor delay. Therefore, materials that have efficient barrier properties at subnanometre thicknesses or that can perform simultaneously as a barrier and liner are critically needed for future technology nodes.

Two-dimensional (2D) materials^2,4,5,6,7 could potentially act as both the diffusion barrier and liner (Fig. 1b). At subnanometre thicknesses, 2D materials are predicted to provide a high energy barrier against Cu diffusion compared with conventional industry-standard materials⁸. Furthermore, the absence of dangling bonds in 2D films reduces interface surface scattering, which may prevent the Cu resistivity from increasing in thinner wires (<15 nm)². The use of monolayer 2D materials for front-end-of-line applications (such as transistors) has been extensively explored^9,10,11, but the integration of single-layer 2D materials into the BEOL remains challenging due to four key growth requirements (Fig. 1b). First, the growth temperature of BEOL materials must be less than 450 °C to prevent damage to the underlying IC structure^12,13. Second, the 2D deposition must be scalable and uniform over the entire area of industry-standardized wafers. Third, layer growth has to be achieved with atomic precision to enable control of the thickness for specific feature sizes in the relevant BEOL stack layer. Finally, the deposition should be conformal (uniform within high-aspect-ratio structures). So far, no growth approach has been able to satisfy all these requirements (Fig. 1c and Supplementary Section 1).

In this Article, we report the wafer-scale growth of crystalline tungsten disulfide (WS₂) layers down to the monolayer regime and thicknesses of 0.7 nm. We use thermal atomic layer deposition (ALD) without plasma, sacrificial layers or post-annealing, which would make the deposition incompatible with the BEOL^{14,15,16,17,18} (see Supplementary Section 1 for a comparison of growth approaches). We show that a single WS₂ layer grown on a silicon (Si)-based substrate can function as both an efficient liner and a Cu barrier. As a liner, single WS₂ layers reduce the resistivity of 10-nm-thick Cu films by more than six orders of magnitude compared with a Cu film directly deposited onto SiO₂. As a barrier, the layers prevent Cu migration under thermal stress and are projected to delay electrical-stress-induced breakdown. We also examine Cu migration through WS₂ films using density functional theory (DFT) simulations, finding that the grain arrangement between layers can help prevent Cu diffusion. Our work shows that single-layer transition-metal dichalcogenides can be integrated as a bifunctional barrier and liner into the BEOL and are a viable route for current and future technology nodes, with a thickness even below that projected for the 0.5-nm-equivalent node due in 2037¹⁹.

Growth of monolayer WS₂ below the BEOL temperature limit

To achieve BEOL-compatible growth of 2D materials, we developed a fully thermal ALD process without any plasma assistance that satisfies all four abovementioned requirements. We focus on WS₂ because recent DFT calculations⁸ indicate that this material system has the highest barrier energy for Cu diffusion among common transition-metal dichalcogenides. WS₂ thin films were synthesized via thermal ALD at the BEOL-compatible temperature of 350 °C using pulsed bis(tert-butylimido)-bis(dimethylamido)-tungsten (W-(NMe₂)₂(N^tBu)₂) as the tungsten source and H₂S gas as the co-reactant (details of the growth are given in Methods). A halide-free W precursor was used to avoid any corrosion and impurity effects and, thus, to improve the film quality by making the process compatible with advanced semiconductor applications. The growth was performed on standard-industry 200-mm wafers (Fig. 1f, top), namely Si substrates with either a 2-nm-thick native SiO₂ layer (SiO_2|nat) or a 100-nm-thick, thermally grown SiO₂ layer (SiO_{2|100 nm}), depending on the characterization requirements. The characteristic in-plane ${{\rm{E}}}_{2{\rm{g}}}^{1}$ and out-of-plane ${{\rm{A}}}_{1{\rm{g}}}$ vibrational Raman modes confirmed that the as-deposited film was crystalline WS₂ (ref. ²⁰). The separation between these peaks, Δω = 61–62 cm⁻¹, corresponds to a single-layer film²⁰ (Fig. 1d). The Raman results were confirmed using cross-sectional transmission electron microscopy (TEM) imaging, which shows a continuous film over the entire TEM field of view (Fig. 1e and Supplementary Section 3). Raman mapping across the entire 200-mm wafer shows an average Δω of 61.3 ± 0.2 cm⁻¹ and demonstrates excellent uniformity with monolayer WS₂ coverage across the wafer (Fig. 1f).

To assess the crystallinity and grain orientation of the films between stacked layers, we deposited a bilayer WS₂ film using the same ALD process_. The crystalline nature of the film is evident in atomically resolved plan-view high-angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) images of the bilayer (Fig. 1g). The STEM results further show that individual layers are polycrystalline with an average grain size of 5–10 nm (Supplementary Section 4). The presence of moiré patterns observed in the STEM images indicates that the grains are not vertically aligned between the two layers, and because both the periodicity and orientation of the moiré patterns vary across the field of view, it can be concluded that the individual grains do not have preferential orientations within a single layer. We later show that this structural morphology likely offers a unique advantage for the diffusion barrier properties of our ALD-grown WS₂. Further spectroscopic and microscopic characterization of the film is detailed in Supplementary Section 5.

Thickness-controlled conformal growth of WS₂

As a third requirement, we demonstrate that the deposited WS₂ thickness can be controlled with single-layer precision by controlling the number of ALD cycles (Fig. 2a). As we increased the number of ALD cycles, the Raman frequency of the ${{\rm{A}}}_{1{\rm{g}}}$ mode shifted towards higher wavenumbers, whereas the ${{\rm{E}}}_{2{\rm{g}}}^{1}$ mode remained fixed, consistent with the layer-by-layer increase of the film thickness²⁰. The Raman results were corroborated with the thickness measurements using cross-sectional TEM and are summarized in Fig. 2b. By establishing a linear correlation of the WS₂ film thickness as a function of the number of ALD cycles, we demonstrated that our approach enables controlled growth of single-layer, bilayer, trilayer and bulk (more than 5-nm-thick) WS₂ films. Raman mapping over 25 × 25 μm² areas confirmed the uniform film thickness and high crystalline quality, as no substantial variations were observed in the mapped Δω values (Fig. 2b) or the full-width at half-maximum of the$\,{{\rm{E}}}_{2{\rm{g}}}^{1}$ and ${{\rm{A}}}_{1{\rm{g}}}$ peaks (Supplementary Section 6).

Fig. 2: Thickness control and conformality of WS₂ ALD growth.

a, Raman spectra of single-layer (1L), bilayer (2L), trilayer (3L) and bulk WS₂ films grown using ALD, with the corresponding cross-sectional phase-contrast TEM images of WS₂ films of different thicknesses. b, Thickness of WS₂ films determined from cross-sectional TEM (red line) and Raman spectra (dashed blue curve), both as a function of the number of ALD growth cycles. Insets: Raman maps of the films. c, Phase-contrast cross-sectional TEM images of trench structures with 2L WS₂ verify conformal growth (false colour used to enhance the contrast). Dashed rectangles indicate areas enlarged in (i) and (ii) to show conformality at the top and at the bottom of the trench.

Finally, conformality is a main BEOL requirement for which most 2D growth techniques fail; however, conformality is required to enable deposition in 3D BEOL structures, particularly in deep trenches with high depth-to-width aspect ratios. Recent research efforts have attempted to address conformality in ALD-grown transition-metal dichalcogenides, but these have been limited to low-aspect-ratio structures (4:1) at the expense of film coverage and quality^21,22. As the future BEOL will include deep structures with trenches reaching aspect ratios approaching 10:1 in the 3-nm technology node and below²³, we demonstrate the compatibility of our growth process with these future sizes. The conformality was determined by comparing the thickness of the WS₂ layer at the bottom and top of the trench (Supplementary Section 7). Figure 2c shows a cross-sectional TEM image of a representative patterned structure with an aspect ratio of 10:1. The enlarged views of the side and bottom of the trench demonstrate uniform conformal deposition of WS₂. Through a systematic analysis over a large area, we measured the conformality of our ALD-grown WS₂ to be >95% for the bilayer structure shown in Fig. 2c and for thicker films shown in Supplementary Section 7. Taken together, our ALD WS₂ growth process fulfils all four main requirements for BEOL integration outlined in Fig. 1b.

ALD-grown WS₂ as an effective liner

We next show that our BEOL-compatible WS₂ films function uniquely well as liners for interconnects: they enable good Cu wettability (important for effective Cu seeding and electroplating) and enhanced conductivity for thin Cu wires, even in the ultrathin (0.7 nm) monolayer limit of WS₂. Cu thin films of various thicknesses ranging from 10 nm to 80 nm were thermally evaporated onto a single-layer WS₂/SiO_{2|100 nm}/Si substrate and a reference SiO_{2|100 nm}/Si substrate without any liner. These films were then patterned into Hall bar structures (Fig. 3a,b) to perform four-terminal point probe measurements. We measured the Cu conductivity of more than 15 devices per Cu film.

Fig. 3: Liner properties of the WS₂ film.

a, Schematic of the device used for resistivity measurements of Cu using WS₂ as a liner. b, Optical micrographs of the liner assessment devices. The electrical connection for the four-terminal measurement is annotated. c, Resistivity of Cu films as a function of film thickness with a WS₂ liner and without a liner (reference). The centres of the circles represent the average resistivity values, based on 13–16 independent devices for each Cu thickness. The error bars show the standard deviation. d, Cumulative distribution of resistivity values for an ~10-nm Cu film with a single-layer WS₂ liner and without a liner (reference). e, SEM and AFM images (inset) of 10-nm-thick Cu films without a liner (reference, top) and with single-layer WS₂ liner (bottom). The root-mean-square roughness, R_rms, is indicated on the respective panels.

Figure 3c shows the thickness-dependent resistivity of the Cu films. For thicker Cu films, where the film integrity can be considered thickness-independent, the devices with and without liners do not exhibit noticeable differences in Cu resistivity (Fig. 3c). An analysis using a combination of the Fuchs–Sondheimer and the Mayadas–Shatzkes models²⁴ to account for surface scattering and grain boundary scattering, respectively, yielded similar values for the device and the reference (Supplementary Section 8). However, for a Cu film thickness of approximately 10 nm, there was a notable drop of more than 6 orders of magnitude in the resistivity between the reference and the WS₂-lined substrates, which had undergone the same Cu deposition. Furthermore, monolayer WS₂ outperformed the industry-standard Ta/TaN stack structure by a factor of ~5 for 10-nm-thick Cu films, despite the monolayer WS₂ liner being much thinner (~0.6 nm) compared with the Ta/TaN stack (5.8 nm), as described in Supplementary Section 8. The results were consistent among devices for the same Cu film, further demonstrating the spatial homogeneity of our films.

To understand the origin of the resistance drop, we conducted scanning electron microscopy (SEM) measurements, which showed that the Cu film morphology was smoother and more continuous for samples with the WS₂ liner compared with the reference sample (Fig. 3e) or indeed that of the Ta/TaN stack (Supplementary Section 8). These results indicate that the WS₂ liner improves Cu wettability, thus enabling continuous and, consequently, less resistive films at lower thicknesses. Atomic force microscopy (AFM) measurements quantified that the surface roughness decreases by more than 50% for Cu films deposited on the WS₂ liner (Fig. 3e). The smoother surface reduced roughness-induced scattering, which in Cu films on WS₂ layers implies less directional scattering at interfaces, leading to a resistance decrease (Supplementary Section 8).

The improvement in Cu resistivity for thinner Cu films is important for future technology nodes, as the Cu wire cross-sectional width is expected to be less than 20 nm. In addition to the absolute change of the resistivity for a fixed Cu thickness, the role of the liner thickness on the interconnect performance must also be considered. For a 20-nm interconnect pitch, the current 4-nm-thick TaN/Ta industry bilayer stack would occupy 40% of the cross-sectional diameter (64% of the cross-sectional area for a wire), implying a lower Cu thickness and higher resistivity. By contrast, our single-layer WS₂ films would only occupy 7% of the cross-sectional diameter (13% of the cross-sectional area), thereby increasing the absolute Cu content and consequently enhancing the Cu conductivity and integrity, as confirmed by our benchmarking results for a Ta/TaN stack.

ALD-grown WS₂ as an effective diffusion barrier

We next focus on testing the performance of our ALD-grown WS₂ films as a Cu diffusion barrier, using two experimental approaches to demonstrate that they prevent Cu migration into the dielectrics and also circuit failure. First, to investigate Cu diffusion under thermal stress, we deposited 100 nm of Cu on both the reference SiO_2|nat/Si wafer (Fig. 4a) and on our single-layer WS₂/SiO_2|nat/Si. The samples were then annealed at 400 °C for 30 min, and the extent of Cu migration and intermixing was characterized through cross-sectional STEM energy-dispersive X-ray spectroscopy (EDS) mapping. A representative STEM bright-field image of the Cu/SiO_2|nat/Si reference (Fig. 4b) shows that in the absence of a barrier, Cu reacted with the substrate and formed three-dimensional core–shell structures with dimensions of 300–500 nm. The corresponding EDS elemental maps reveal substantial intermixing between Cu, O and Si, with the outer layer consisting predominantly of Si and O. The inner region comprises mostly Si and Cu. Similar intermixing and morphological disruption are seen on trench structures defined by electron-beam lithography (EBL) on a similar substrate (Fig. 4c). On the other hand, no reaction or intermixing among the layers was observed in the sample with single-layer ALD-grown WS₂ between SiO₂ and Cu (Fig. 4d), indicating that WS₂ acts as an efficient diffusion barrier, as seen in the intact structures in bright-field STEM images in Fig. 4e,f. Similar results are seen in EBL-defined trench structures (analogous to BEOL trenches), as shown in Fig. 4c,f and Supplementary Section 9. These results were confirmed using grazing-incidence X-ray diffraction (GIXRD) before and after annealing (Fig. 4g–i). Before the annealing, only Cu peaks were observed in the GIXRD spectra of both the reference and the sample containing the WS₂ layer. After annealing, the Cu peak decreased notably for the reference sample, and it was replaced by a strong Cu₃Si peak (Fig. 4h), showing substantial Cu migration and intermixing with the underlying Si substrate. By contrast, for the single-layer WS₂/SiO_2|nat/Si, the Cu peaks were retained post-annealing, denoting no Cu–Si intermixing (Fig. 4i). Furthermore, dynamic secondary-ion mass spectrometry (SIMS) results (Supplementary Section 9) confirm that Cu penetrated deep into the Si after the annealing of samples without a barrier, whereas a single-layer WS₂ barrier prevented this diffusion.

Fig. 4: WS₂ films as a diffusion barrier.

a, Schematic of the Cu/SiO_2|nat/Si structures used for the thermal stress tests. b,c, Elemental distribution maps of Cu/SiO_2|nat/Si after the thermal stress on a plain Si substrate (b) and on a substrate with trench structure (c), with EDS elemental mapping of Cu as inset. d, Schematic of the Cu/single-layer WS₂/SiO_2|nat/Si structures used for assessing WS₂ film as diffusion barriers under thermal stress. e,f, Elemental distribution maps of Cu/single-layer WS₂/SiO_2|nat/Si after the thermal stress on a plain Si substrate (e) and on a substrate with trench structure (f), with EDS elemental mapping of Cu as inset. g–i, GIXRD analysis before and after the thermal stress. g, Reference Cu and Cu₃Si peaks (Methods). h,i, GIXRD spectra for the Cu/SiO_2|nat/Si (h) and Cu/single-layer WS₂/SiO_2|nat/Si (i), both before and after annealing. j, Device structure used for electrical breakdown measurements to assess WS₂ films as diffusion barriers under electrostatic stress. k, Measured characteristic breakdown time τ as a function of applied voltage for single-layer WS₂ and a reference without a barrier. Dashed lines show extracted E model projections for the reference (orange) and a single-layer WS₂ barrier (green). Each τ value was extracted from 5–10 breakdown-time measurements in different junctions. Error bars show the standard deviation of log₁₀ [τ (s)]. Individual breakdown-time data points are displayed in Supplementary Section 10. l, Cumulative distribution of the projected breakdown time for an electrical stress of 8 MV cm⁻¹ from the measurements. as-dep., as deposited; BF, bright field; ref., reference.

Finally, we conducted time-of-flight (ToF) SIMS, SEM and EDS analyses to investigate the thickness dependence of this barrier behaviour and to provide a comparative analysis with the industry standard. Samples of the same structure with WS₂ barriers of different thicknesses, an ALD-grown TaN barrier (1.6 nm), and a reference without a barrier were subjected to an anneal process optimized to produce the onset of observable changes in the sample with single-layer WS₂, that is 45 min at 500 °C. The results (Supplementary Section 9) show that single-layer WS₂ outperformed thicker 1.6-nm TaN in suppressing intermixing between Si and Cu and preventing morphological disruption of the Cu film. They also demonstrate scalable barrier performance with WS₂ thickness, as the minor changes resulting from the annealing process observed in the sample with single-layer WS₂ were absent for two-layer and thicker WS₂ barriers.

In addition to the thermal stress measurements, our second approach focuses on measuring the time-dependent dielectric breakdown^2,4,5,8 to test the performance of the barrier of the ALD-grown WS₂ films under electrical stress. Upon growth of the WS₂ films, the devices shown in Fig. 4j were fabricated using an all-dry process that was agnostic to the surface chemistry and, thus, prevented material-specific chemical reactions. The Cu/WS₂/SiO_{2|100 nm}/Si junctions were subjected to a fixed voltage V, and the current was monitored in real time until a breakdown occurred in the form of a sudden increase in current, corresponding to dielectric breakdown or Cu migration into the dielectric. The breakdown time t_bd was recorded for 50 junctions and for a range of applied voltages, which enabled us to determine the relation between V and t_bd in the standard E model approximation, ${t}_{{\rm{bd}}}\propto \exp \left(-\gamma V\right)$, whereby γ is known as the acceleration factor (Supplementary Section 10), which delivers more conservative lifetime estimates compared with other common approximations⁵ (Methods and Supplementary Section 10).

Figure 4k,l compares the devices with single-layer WS₂ with a reference device that does not contain a barrier. For each device and each value of applied voltage, the cumulative distribution of the several t_bd values measured were fitted with a Weibull cumulative distribution function, $F\left({t}_{\mathrm{bd}}\right)=1-\exp [-{\left({t}_{\mathrm{bd}}/\tau \right)}^{\beta }],$ to extract the characteristic breakdown time τ, where β is the shape parameter of the function, and consequently γ. Our results show that γ is higher for devices with WS₂, at 1.10 ± 0.05 V⁻¹, compared with 0.8 ± 0.1 V⁻¹ for the reference device without a barrier. This higher value means that for lower electrostatic stresses, such as the ones relevant for normal operation, junctions with a WS₂ barrier have a higher projected lifetime than the reference (Supplementary Section 10). A projection of the measured breakdown times to 8 MV cm⁻¹ using the power law and the extracted acceleration factors (Fig. 4l) shows that the WS₂ barriers are projected to extend the characteristic breakdown time τ to $3\times {10}^{6}\,{\rm{s}}$ for single-layer WS₂, compared with $2\times {10}^{5}\,{\rm{s}}$ for the reference. Taken together, our tests under thermal and electrical stresses confirm that our ALD-grown WS₂ films are effective as Cu diffusion barriers, even in a monolayer regime.

Furthermore, we conducted a similar study for WS₂ samples of different thicknesses to establish the thickness dependence of barrier performance under an electrical stress and compared these with TaN barriers (Supplementary Section 10). This study revealed that single-layer WS₂ performed much like thicker 1.6-nm TaN barriers, whereas thicker WS₂ barriers clearly outperformed TaN with a projected breakdown time that scaled with WS₂ thickness.

Influence of defect alignment on Cu diffusion through WS2 barriers

To better understand Cu diffusion in our WS₂ films, we conducted simulations to examine Cu diffusion through ideal and defective (finite-grain) WS₂ layers using climbing image-nudged elastic band calculations. The resulting diffusion pathways are shown in Fig. 5a–c, and the corresponding energy profiles in Fig. 5d. The first pathway represents the energy profile for Cu diffusion through an ideal (defect-free) WS₂ layer, which reveals an energy barrier $\Delta E$ (the difference between the highest and lowest energy points in the diffusion path) of $5.6\,\mathrm{eV}$. Within the same pathway, the energy barrier for Cu diffusion between ideal WS₂ layers (15 Å into the pathway of Fig. 5a with energy profile shown in Fig. 5d) was found to be $0.5\,\mathrm{eV}$. With defective WS₂ layers, atomic vacancies of 1W and 2S were generated to mimic a small grain boundary (inset of Fig. 5b), where Cu is found to be favourably adsorbed at the W vacancy site with an adsorption energy ${E}_{\mathrm{ads}}=-4.5\,\mathrm{eV}$. This energy value represents the energy required for Cu to break away from that adsorption site, regardless of the type of layers Cu needs to diffuse through (as illustrated in Fig. 5d). As depicted in Fig. 5b, when the defects (or grain boundaries) are aligned between WS₂ layers, Cu requires only a minimal amount of energy $(\Delta E=0.8\,\mathrm{eV})$ to diffuse from one layer to the next. Throughout the pathway, there is only one instance where a maximum energy barrier of$\,4.5\,\mathrm{eV}$ occurs, making it comparable in effectiveness with a defective single layer (Supplementary Section 11). By contrast, within a bilayer structure where defects on each layer are not in close proximity to each other (Fig. 5c), Cu requires a higher energy to traverse an ideal bottom WS₂ layer (indicated by solid blue markers in Fig. 5d(i), $\Delta E=7.8\,\mathrm{eV}$) or diffuse between layers (depicted by hollow blue markers in Fig. 5d(ii), $\Delta E=1.7\,\mathrm{eV}$).

Fig. 5: Computational diffusion barriers for Cu through WS₂.

a–c, Side and top views of Cu diffusion. a, Ideal WS₂ bilayer. b, Defective WS₂ bilayer with aligned defects. Inset: the generated defect. c, Defective WS₂ layer over an ideal WS₂ layer mimicking a bilayer with misaligned grains. There is another pathway (dashed blue line) for intralayer migration. d, Corresponding energy profiles calculated for the different pathways. Visualization in a–c created with VESTA⁴⁷.

In the context of conventional diffusion barriers, Cu diffusion through a film typically occurs preferentially along grain boundaries and crystal defects². However, for multilayer ALD-grown WS₂ films, the random misalignment between layers reduces the likelihood of the superposition of these paths, including Cu migration through the film. Therefore, our simulations indicate that the distinctive structure of our multilayered WS₂ offers further benefits for applications that do not need a monolayer film. This result is in accordance with the thickness scaling seen in our barrier characterization under thermal and electrical stress.

Conclusions

We have reported on a scalable approach for creating ultrathin WS₂ films that fulfil the requirements for BEOL integration at sub-5-nm technology nodes and can function as both interconnect barriers and liners. The ALD growth process produces scalable and uniform films over 200-mm wafers without the need to transfer WS₂. The film thickness is controlled with single-layer precision, from monolayer to bulk thicknesses, by varying the number of ALD cycles. We have shown that the deposition is highly conformal, with conformality of >95% achieved for high-aspect-ratio structures such as those predicted for sub-5-nm technology nodes. The inclusion of our WS₂ films as liners for Cu films leads to a resistivity decrease in the metal wire, and the films also acts as a diffusion barrier, preventing Cu migration and dielectric breakdown under thermal and electrical stresses.

Investigating the 2D interface at a microscopic level could provide a better understanding of the relation between crystalline grains and failure mechanisms. Obtaining more control over the grain structure during or after growth could also lead to further improvement of the liner and barrier properties. A previous study of hexagonal boron nitride²⁵ indicated that van der Waals stacking of 2D films can improve resistance to electromigration, which may be another parameter to consider for our films. More broadly, other 2D films as well as substrate materials beyond SiO₂ could be explored with a similar approach for further specialized use or better compatibility with specific integration requirements. For instance, low-κ dielectric materials (such as those based on porous SiO₂; ref. ²⁶) may be affected by the ALD processes, which could be addressed by adjusting the growth cycle sequences. Future requirements may involve material-selective growth to confine the growth to specific regions of the interconnect structure, such as using self-assembled monolayers as protective layers during growth²⁷.

Methods

WS₂ ALD growth process

WS₂ thin films were synthesized in a thermal ALD reactor (Atomic-Premium ALD, CN1). Bis(tert-butylimido)-bis(dimethylamido)-tungsten (W-(NMe₂)₂(N^tBu)₂; Sigma-Aldrich) was used as the tungsten (W) source, and H₂S gas as the co-reactant. Each cycle consisted of a W precursor pulse (2 s, with N₂ as the carrier gas), followed by N₂ and O₃ pulses (75 s), a H₂S gas pulse (60 s) and an N₂ pulse (30 s). The substrate temperature was 350 °C. The growth rate was 0.65 Å per cycle, and repeating such ALD cycles resulted in the growth of the desired WS₂ layers on Si-based substrates. WS₂ films of various thickness were also deposited on conformal structures having an aspect ratio of 10:1 provided by Applied Materials Inc. In samples used for studying the thickness-dependent and time-dependent dielectric breakdown, the substrate temperature was 300 °C.

Raman characterization of WS₂ films

Raman spectroscopy measurements were carried out on the WS₂ thin films using a Horiba Jobin-Yvon HR800 Raman instrument with a laser excitation wavelength of 488 nm. The laser was set to 2 mW power with a 1 μm² spot size. The individual Raman modes were deconvolved using Lorentzian fitting.

TEM sample preparation and imaging

Electron-transparent samples for cross-sectional TEM imaging were prepared using the in situ lamella lift-off method, and plan-view samples for STEM imaging were prepared through the standard transfer process: spin-coating poly(methyl methacrylate), KOH etching and adhesion to a holey carbon grid. Atomically resolved STEM images were acquired with a JEOL JEM-ARM200F equipped with a cold field emission gun and a fifth-order ASCOR aberration corrector operated at 200 kV and a probe convergence angle α of ~31 mrad. Phase-contrast high-resolution TEM images, and STEM/EDS images were acquired with a FEI Talos operated at 200 kV.

Fabrication of Hall bar devices for liner characterization

Hall bar devices, 50 µm wide and 65 µm long, were fabricated by a reverse etching process. Cu films with various thicknesses (10 mm, 15 mm, 20 mm, 30 mm, 40 mm, 50 mm and 80 nm) were deposited at a slow rate (0.15 Å s⁻¹ for the first 20 nm and then 0.5 Å s⁻¹ for the remaining thickness if any) on a single-layer WS₂ film on SiO₂/Si, on an unlined SiO₂/Si substrate (reference) and on a Ta/TaN/SiO₂/Si structure with a thermal and electron-beam evaporator (AJA). The Ta/TaN bilayer consisted of 2.7 nm of TaN deposited via ALD and 3.1 nm of Ta deposited via sputtering using a sputter system (AJA). We chose a slow Cu growth rate to reduce the kinetic damage to the underlying WS₂ films. Cu-coated samples were spin-coated with a photoresist (Shipley S1805) at 5,500 rpm for 1 min and then baked at 115 °C for 1 min. The Hall bar structures were patterned on the photoresist with a laser writer (Microtech LW-405). The exposed samples were developed in Microposit MF-319 developer for 40 s. A 0.05 M ammonium persulfate solution was used to etch away the exposed Cu area, while the Hall bar device regions remained protected by the unexposed photoresist. The WS₂ was not etched. Before the electrical resistivity measurement, the photoresist was lifted off by rinsing with acetone and isopropyl alcohol. The Cu thickness was obtained by profiling edges using a Bruker AFM and a Park Systems AFM in four locations for each chip.

Hall bar measurement for liner characterization

The patterned devices were bonded with Al wires to a leadless chip carrier. The four-terminal resistance measurements were performed using a physical property measurement system (Quantum Design) and a Keithley Source Meter for more than ten devices for each Cu thickness, with connections as shown in Fig. 3b. The resistivity was extracted from the four-terminal resistivity and the physical dimensions of the Hall bar channel.

Assessment of Cu migration under thermal stress

To evaluate the Cu thermal stress properties, we thermally evaporated 100 nm Cu onto SiO_2|nat/Si (reference) and single-layer WS₂ onto SiO_2|nat/Si. The samples were post-annealed at 400 °C for 30 min under an Ar atmosphere at 2 Torr. The as-deposited and post-annealed samples were used to evaluate the performance of single-layer WS₂ films as Cu diffusion barriers under thermal stress using X-ray diffraction, STEM/EDS and SIMS.

Fabrication of trench structures for assessing Cu migration under thermal stress

Trenches of width 100 nm, 200 nm, 500 nm and 1 μm were patterned onto Si substrates using an EBL system (Raith). The trenches were then etched in an inductively coupled plasma reactive-ion etching system (Oxford Instruments) using a combination of SF₆ and C₄F₈ as reactive gases. The trenches were measured to be 250 nm deep using AFM. On some trench samples, the ALD process was applied to grow single-layer WS₂ onto the structures; other trench samples were left without a barrier as a reference. Next, 300 nm of Cu was deposited onto all samples using thermal evaporation. All samples then underwent annealing (500 °C, Ar under 0.5 Torr for 45 min). The resulting samples were then imaged using optical imaging, TEM and EDS.

GIXRD

GIXRD (ω = 5°) was carried out for the as-deposited and annealed Cu (100 nm)/SiO_2|nat/Si, with and without a single-layer WS₂ film at the Cu/Si interface, using Bruker D8 Advance, equipped with Cu Kα radiation of wavelength 1.542 Å. The reference X-ray diffraction peaks were taken from the Joint Committee on Powder Diffraction Standards expected for Cu (reference 00-004-0836) and Cu₃Si (reference 00-051-0916).

Fabrication of devices for breakdown testing due to bias-induced Cu migration

The devices used for electrical breakdown measurements to assess the performance of WS₂ films as Cu diffusion barriers were fabricated in an all-dry fabrication process. Single-layer WS₂ films were deposited onto 2 cm × 2 cm SiO_{2|100 nm}/Si coupons. In addition, a SiO_{2|100 nm}/Si reference sample from the same wafer was subjected to a thermal treatment reproducing the temperature conditions of this growth without WS₂ deposition. Following this, we affixed stainless steel shadow masks onto the samples and the reference. The shadow masks defined arrays of 150 µm × 150 µm junctions. The samples were placed inside a thermal evaporator (AJA) together, and a 100-nm Cu film was evaporated onto the samples through the shadow masks, at a rate of 0.2 Å s⁻¹ for the first ~10 nm and 0.5 Å s⁻¹ for the remaining thickness, so as to obtain 10 × 10 arrays of Cu/WS₂/SiO_{2,100 nm}/Si junctions (Cu/SiO_{2|100 nm}/Si for the reference). The back surfaces of the samples were mechanically scratched to expose the p-doped Si and placed in a thermal evaporator (Lesker) where 100 nm of Al was evaporated onto the back to form contacts with the Si substrates.

Electrical measurement of breakdown devices

The electrical breakdown of the devices was measured, as in previous reports^4,5,8, in an electrical probe station at room temperature. For each junction, the Cu gate was contacted while the substrate was grounded, and a fixed voltage was applied while the current was recorded. Breakdown was defined as the point at which the current reached a threshold of 0.9 mA (typically as a sudden jump); the time elapsed from voltage application to breakdown was recorded. The threshold was adjusted in the thickness-dependence study to account for the different post-breakdown currents and capacitive spikes (0.1 mA for TaN and single-layer WS₂ and 0.5 mA for three- and four-layer WS₂ as it was affected by capacitive charging). A range of voltage values was applied for each sample, such that a relation between t_bd and V could be extracted while keeping the measurement times practical. Each value was repeated 5–10 times for each sample to account for possible deviations (3–5 for the TaN reference due to fabrication limitations). More details of the data and error analysis are given in Supplementary Section 10.

Computation of energy profiles for Cu migration through WS₂ layers

All geometry optimizations and climbing image-nudged elastic band²⁸ calculations were performed with VASP software^29,30,31,32 using DFT³³ with projector augmented wave pseudopotentials³⁴ and the Perdew–Burke–Ernzerhof exchange-correlation functional³⁵. Both monolayer and bilayer WS₂ were generated by cleaving a pre-optimized WS₂ unit cell along the (001) plane and building a 4 × 4 supercell with layers centred in a 20 Å vacuum. A 2 × 2 × 1 Г-centred k-point mesh was then used to sample the Brillouin zone, and a cutoff energy of 400 eV was applied. Gaussian smearing with a width of 0.05 eV was used to specify how the electron partial occupancies were set for each orbital. All geometries were optimized with fixing cells until the forces on all atoms were below 0.02 eV Å⁻¹. The DFT-D3 method in Grimme³⁶ was applied to estimate the van der Waals corrections among atoms. Spin polarization was also employed due to the odd number of electrons.

AFM

AFM imaging was performed to extract roughness parameters and film thicknesses for Cu films. The images were acquired on Bruker and Parks AFM systems in tapping mode. Images were processed with the software Gwyddion and Nanoscope.

Scanning electron microscopy

SEM images were obtained using a FE-SEM Hitachi Regulus system in image mode at 1 kV.

ToF-SIMS

The ToF-SIMS elemental analysis was performed using a focused ion beam microscope (TESCAN GAIA 3) connected to a mass spectrometer (Tofwerk). The primary beam was a 30 keV, 200 pA Ga⁺ beam. The mass spectra were collected in positive polarity mode. A 128 × 128 pixel hyperspectral map was recorded over the analysis area of 30 × 30 µm² using a dwell time of 12 µs. The Si peak at 28 m/z and the Cu peak at 63 m/z were extracted from the spectra and shown in the figures as intensity maps. The vertical map of the first ten frames from the surface is displayed below each spatial map.

SEM imaging and EDS elemental mapping

SEM images and EDS maps were acquired on a Zeiss Sigma 300, equipped with an Oxford Ultim Max 65 mm² SDD operated at 5 kV. Images shown were collected from the in-lens secondary electron detector.