Gate-Dielectric Engineering with an Ultrathin Silicon Oxide Interfacial Dipole Layer for Low-Leakage Oxide-Semiconductor Memories

Journal:
Nano Letters
Published:
DOI:
10.1021/acs.nanolett.5c05167
Affiliations:
4
Authors:
14
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Institutions Authors Share
Stanford University, United States of America (USA)
11.000000
11.000000
 0.79
TSMC North America, United States of America (USA)
2.000000
 0.14
TSMC, Taiwan
1.000000
 0.07
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