A Universal Implementation Approach for Multivalued Logic Gates Based on Negative Transconductance in Series-Connected Two-Dimensional Transistors

Journal:

ACS Nano

Published:

2025-07-15

DOI:

10.1021/acsnano.5c04182

Affiliations:

4

Authors:

7

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Institutions	Authors	Share
Shenzhen Institutes of Advanced Technology (SIAT), CAS, China	3.000000	0.43
CNRS International NTU THALES Research Alliance (CINTRA), Singapore	2.000000	0.29
Nanyang Technological University (NTU), Singapore	1.500000	0.21
Institute of Electronics, Microelectronics and Nanotechnology (IEMN), France	0.500000	0.07

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