Concurrent/Parallel Systems and Technologies
Summary
Concurrent and parallel systems span from tightly integrated multicore and many-core processors to distributed clusters and cloud infrastructures. At the hardware level, advances in pipelining, superscalar execution and simultaneous multithreading have exploited instruction-level parallelism, while modern system-on-chip designs integrate heterogeneous cores, GPUs and accelerators to deliver high throughput. Memory hierarchies combining multi-level caches with predictable arbitration and partitioning techniques address latency and contention in shared hardware. Virtualisation and hypervisor frameworks enable time- and space-sharing of compute and I/O resources, supporting mixed-criticality and multi-tenant deployments. On the software side, task- and data-parallel programming models—from SIMD extensions to dynamic task graphs—allow developers to express fine-grained concurrency. Runtime systems and formal analysis tools for scheduling, memory consistency and performance modelling underpin the design of reliable, real-time and high-performance applications. Together, these cross-layer innovations drive domains as diverse as embedded real-time control, enterprise services, scientific simulation and data-centre operations.
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Research from all publishers
A comprehensive survey of interference-reduction techniques categorises hardware partitioning, cache and bus arbitration policies, I/O throttling and software isolation methods. It evaluates their integration into formal schedulability analyses, guiding designers of mixed-criticality multicore platforms towards tighter worst-case bounds without sacrificing average-case performance. A detailed study of Arm’s Memory System Resource Partitioning and Monitoring (MPAM) specification instantiates its regulators to model fine-grained memory contention. By quantifying worst-case access delays under different QoS configurations, the work offers practical insights for time-predictable commercial SoCs. In the I/O virtualisation domain, a framework leveraging ARM’s QoS-400 regulators controls device DMA and global memory traffic within a hypervisor. Experiments show up to eight-fold reductions in latency variability for virtualised real-time workloads, demonstrating that coordinated QoS enforcement can reconcile I/O sharing with strict timing guarantees.
Concurrent/Parallel Systems and Technologies publication trend
The graph below shows the total number of articles in concurrent/parallel systems and technologies across all publications each year (not limited to Nature Index journals).
Technical terms
Instruction-level parallelism (ILP): The parallel execution of multiple machine instructions within a single processor cycle, enabled by pipelining and multiple functional units.
Mixed-criticality: A design paradigm in which tasks of differing safety or performance importance co-exist on shared hardware under enforced isolation.
Schedulability analysis: Formal methods to verify that a set of real-time tasks meets their deadlines under specified resource models and arbitration policies.
Quality-of-Service (QoS) regulator: Mechanism—hardware or software—that allocates access to shared resources (e.g. memory bandwidth) to bound contention and ensure predictability.
Hypervisor: A virtualisation layer that abstracts physical hardware, enforces isolation and mediates scheduling for multiple guest operating systems or partitions.
DMA (Direct Memory Access): A mechanism allowing devices to transfer data to or from memory independently of the CPU, which can introduce contention on shared buses.
References
- A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms. IEEE Access (2022).
- Analyzing Arm's MPAM From the Perspective of Time Predictability. IEEE Transactions on Computers (2022).
- An I/O Virtualization Framework With I/O-Related Memory Contention Control for Real-Time Systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2022).
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